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linux/drivers/net/phy/icplus.c

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net: phy: Convert some PHY and MDIO driver files to SPDX headers Where the license text and the MODULE_LICENSE() value agree, convert to using an SPDX header, removing the license text. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-01-21 19:05:50 +01:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
net: phy: icplus: allow configuring the interrupt function on IP101GR The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA Ethernet PHY. Due to it's limited amount of pins the RXER (receive error) and INTR32 (interrupt) functions share pin 21. By default the PHY is configured to output the "receive error" status on pin 21. Depending on the board layout and requirements we may want to re-configure the PHY to output the interrupt signal there. The mode of pin 21 can be configured in the "Digital I/O Specific Control Register" (register 29), bit 2: - 0 = RXER function - 1 = INTR(32) function Depending on the devicetree configuration we will now: - change the mode to either ther RXER or INTR32 function - keep the SEL_INTR32 value set by the bootloader (default) if no configuration is provided (to ensure that we're not breaking existing boards) - error out if conflicting configuration is given (RXER and INTR32 mode are enabled at the same time) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:59 +01:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
Replace <asm/uaccess.h> with <linux/uaccess.h> globally This was entirely automated, using the script by Al: PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*<asm/uaccess.h>' sed -i -e "s!$PATT!#include <linux/uaccess.h>!" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h) to do the replacement at the end of the merge window. Requested-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-12-24 11:46:01 -08:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
phy: IC+101G and PHY_HAS_INTERRUPT flag This patch adds the PHY_HAS_INTERRUPT flag for IC+101 device series. Also the patch does a simple dity-up to signal that the driver actually is for IP101A LF and IP101G devices. In fact, these are two similar PHYs that have the same IDs and mainly differ for the EEE capability supported in the G series. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-02-21 21:26:28 +00:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
phy: IC+101G and PHY_HAS_INTERRUPT flag This patch adds the PHY_HAS_INTERRUPT flag for IC+101 device series. Also the patch does a simple dity-up to signal that the driver actually is for IP101A LF and IP101G devices. In fact, these are two similar PHYs that have the same IDs and mainly differ for the EEE capability supported in the G series. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-02-21 21:26:28 +00:00
net: phy: icplus: use the BIT macro where possible This makes the code consistent by using the BIT() macro instead of manual bit-shifting for some of the fields. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:56 +01:00
phy: IC+101G and PHY_HAS_INTERRUPT flag This patch adds the PHY_HAS_INTERRUPT flag for IC+101 device series. Also the patch does a simple dity-up to signal that the driver actually is for IP101A LF and IP101G devices. In fact, these are two similar PHYs that have the same IDs and mainly differ for the EEE capability supported in the G series. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-02-21 21:26:28 +00:00
net: phy: icplus: use the BIT macro where possible This makes the code consistent by using the BIT() macro instead of manual bit-shifting for some of the fields. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:56 +01:00
net: phy: icplus: add MDI/MDIX support for IP101A/G Implement the operations to set desired mode and retrieve the current mode. This feature was tested with an IP101G. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:50 +01:00
icplus: fix interrupt for IC+ 101A/G and 1001LF This patch fixes and adds the irq handler for the IC+ 101A/G where we need to read the reg17 to clean the irq. Also remove the flag for the 1001LF where no interrupt can be used for this device. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-17 21:16:40 +00:00
net: phy: icplus: add config_intr callback Move IRQ configuration for IP101A/G from config_init to config_intr callback. Reasons: 1. This allows phylib to disable interrupts if needed. 2. Icplus was the only driver supporting interrupts w/o defining a config_intr callback. Now we can add a phylib plausibility check disabling interrupt mode if one of the two irq-related callbacks isn't defined. I don't own hardware with this PHY, and the change is based on the datasheet for IP101A LF (which is supposed to be register-compatible with IP101A/G). Change is compile-tested only. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-11 21:49:12 +01:00
net: phy: icplus: rename IP101A_G_NO_IRQ to IP101A_G_IRQ_ALL_MASK The datasheet uses the name "All Mask" for this bit. Change the name of our #define to be consistent with the datasheet. While here also replace the tab between the #define and IP101A_G_IRQ_ALL_MASK with a space. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:57 +01:00
net: phy: icplus: implement .did_interrupt for IP101A/G The IP101A_G_IRQ_CONF_STATUS register has bits to detect which interrupts have fired. Implement the .did_interrupt callback to let the PHY core know whether the interrupt was for this specific PHY. This is useful for debugging interrupt problems with 32-pin IP101GR PHYs where the interrupt line is shared with the RX_ERR (receive error status) signal. The default values are: - RX_ERR is enabled by default (LOW means that there is no receive error) - the PHY's interrupt line is configured "active low" by default Without any additional changes there is a flood of interrupts if the RX_ERR/INTR32 signal is configured in RX_ERR mode (which is the default). Having a did_interrupt ensures that the PHY core returns IRQ_NONE instead of endlessly triggering the PHY state machine. Additionally the kernel will report this after a while: irq 28: nobody cared (try booting with the "irqpoll" option) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:58 +01:00
net: phy: icplus: add MDI/MDIX support for IP101A/G Implement the operations to set desired mode and retrieve the current mode. This feature was tested with an IP101G. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:50 +01:00
net/phy: add IC+ IP101A and support APS. This patch adds the IC+ IP101A Single port 10/100 PHY and supports the APS (i.e. power saving mode while link is down) for both IP1001 and IP101A (where this mode is supported). Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-09-06 20:14:50 +00:00
net: phy: icplus: split IP101A/G driver Unfortunately, the IP101A and IP101G share the same PHY identifier. While most of the functions are somewhat backwards compatible, there is for example the APS_EN bit on the IP101A but on the IP101G this bit reserved. Also, the IP101G has many more functionalities. Deduce the model by accessing the page select register which - according to the datasheet - is not available on the IP101A. If this register is writable, assume we have an IP101G. Split the combined IP101A/G driver into two separate drivers. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:46 +01:00
net: phy: icplus: allow configuring the interrupt function on IP101GR The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA Ethernet PHY. Due to it's limited amount of pins the RXER (receive error) and INTR32 (interrupt) functions share pin 21. By default the PHY is configured to output the "receive error" status on pin 21. Depending on the board layout and requirements we may want to re-configure the PHY to output the interrupt signal there. The mode of pin 21 can be configured in the "Digital I/O Specific Control Register" (register 29), bit 2: - 0 = RXER function - 1 = INTR(32) function Depending on the devicetree configuration we will now: - change the mode to either ther RXER or INTR32 function - keep the SEL_INTR32 value set by the bootloader (default) if no configuration is provided (to ensure that we're not breaking existing boards) - error out if conflicting configuration is given (RXER and INTR32 mode are enabled at the same time) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:59 +01:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: add PHY counter for IP101G The IP101G provides three counters: RX packets, CRC errors and symbol errors. The error counters can be configured to clear automatically on read. Unfortunately, this isn't true for the RX packet counter. Because of this and because the RX packet counter is more likely to overflow, than the error counters implement only support for the error counters. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:49 +01:00
net: phy: icplus: use PHY_ID_MATCH_MODEL() macro Simpify the initializations of the structures. There is no functional change. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:42 +01:00
net: phy: icplus: allow configuring the interrupt function on IP101GR The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA Ethernet PHY. Due to it's limited amount of pins the RXER (receive error) and INTR32 (interrupt) functions share pin 21. By default the PHY is configured to output the "receive error" status on pin 21. Depending on the board layout and requirements we may want to re-configure the PHY to output the interrupt signal there. The mode of pin 21 can be configured in the "Digital I/O Specific Control Register" (register 29), bit 2: - 0 = RXER function - 1 = INTR(32) function Depending on the devicetree configuration we will now: - change the mode to either ther RXER or INTR32 function - keep the SEL_INTR32 value set by the bootloader (default) if no configuration is provided (to ensure that we're not breaking existing boards) - error out if conflicting configuration is given (RXER and INTR32 mode are enabled at the same time) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:59 +01:00
net: phy: icplus: add PHY counter for IP101G The IP101G provides three counters: RX packets, CRC errors and symbol errors. The error counters can be configured to clear automatically on read. Unfortunately, this isn't true for the RX packet counter. Because of this and because the RX packet counter is more likely to overflow, than the error counters implement only support for the error counters. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:49 +01:00
net: phy: icplus: allow configuring the interrupt function on IP101GR The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA Ethernet PHY. Due to it's limited amount of pins the RXER (receive error) and INTR32 (interrupt) functions share pin 21. By default the PHY is configured to output the "receive error" status on pin 21. Depending on the board layout and requirements we may want to re-configure the PHY to output the interrupt signal there. The mode of pin 21 can be configured in the "Digital I/O Specific Control Register" (register 29), bit 2: - 0 = RXER function - 1 = INTR(32) function Depending on the devicetree configuration we will now: - change the mode to either ther RXER or INTR32 function - keep the SEL_INTR32 value set by the bootloader (default) if no configuration is provided (to ensure that we're not breaking existing boards) - error out if conflicting configuration is given (RXER and INTR32 mode are enabled at the same time) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:59 +01:00
net: phy: icplus: add PHY counter for IP101G The IP101G provides three counters: RX packets, CRC errors and symbol errors. The error counters can be configured to clear automatically on read. Unfortunately, this isn't true for the RX packet counter. Because of this and because the RX packet counter is more likely to overflow, than the error counters implement only support for the error counters. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:49 +01:00
net: phy: icplus: allow configuring the interrupt function on IP101GR The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA Ethernet PHY. Due to it's limited amount of pins the RXER (receive error) and INTR32 (interrupt) functions share pin 21. By default the PHY is configured to output the "receive error" status on pin 21. Depending on the board layout and requirements we may want to re-configure the PHY to output the interrupt signal there. The mode of pin 21 can be configured in the "Digital I/O Specific Control Register" (register 29), bit 2: - 0 = RXER function - 1 = INTR(32) function Depending on the devicetree configuration we will now: - change the mode to either ther RXER or INTR32 function - keep the SEL_INTR32 value set by the bootloader (default) if no configuration is provided (to ensure that we're not breaking existing boards) - error out if conflicting configuration is given (RXER and INTR32 mode are enabled at the same time) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:59 +01:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
net: phy: icplus: fix checkpath error Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2013-12-17 21:38:08 -08:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
phy: Add an mdio_device structure Not all devices attached to an MDIO bus are phys. So add an mdio_device structure to represent the generic parts of an mdio device, and place this structure into the phy_device. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-01-06 20:11:16 +01:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
phy: Add an mdio_device structure Not all devices attached to an MDIO bus are phys. So add an mdio_device structure to represent the generic parts of an mdio device, and place this structure into the phy_device. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-01-06 20:11:16 +01:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
phy: Add an mdio_device structure Not all devices attached to an MDIO bus are phys. So add an mdio_device structure to represent the generic parts of an mdio device, and place this structure into the phy_device. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-01-06 20:11:16 +01:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
phy: Add an mdio_device structure Not all devices attached to an MDIO bus are phys. So add an mdio_device structure to represent the generic parts of an mdio device, and place this structure into the phy_device. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-01-06 20:11:16 +01:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
phy: Add an mdio_device structure Not all devices attached to an MDIO bus are phys. So add an mdio_device structure to represent the generic parts of an mdio device, and place this structure into the phy_device. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-01-06 20:11:16 +01:00
netdev/phy/icplus: Use mdiobus_write() and mdiobus_read() for proper locking. Usually you have to take the bus lock. Why not here too? I saw this when working on something else. Not even compile tested. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Greg Dietsche <Gregory.Dietsche@cuw.edu> Cc: "Uwe Kleine-Konig" <u.kleine-koenig@pengutronix.de> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-09-30 12:17:48 +00:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
phy: Add an mdio_device structure Not all devices attached to an MDIO bus are phys. So add an mdio_device structure to represent the generic parts of an mdio device, and place this structure into the phy_device. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-01-06 20:11:16 +01:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
phy: Add an mdio_device structure Not all devices attached to an MDIO bus are phys. So add an mdio_device structure to represent the generic parts of an mdio device, and place this structure into the phy_device. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-01-06 20:11:16 +01:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
net/phy: add IC+ IP101A and support APS. This patch adds the IC+ IP101A Single port 10/100 PHY and supports the APS (i.e. power saving mode while link is down) for both IP1001 and IP101A (where this mode is supported). Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-09-06 20:14:50 +00:00
netdev/phy/icplus: Correct broken phy_init code The code for ip1001_config_init() was totally broken if you were not using RGMII. Instead of returning an error code or zero it actually returned the value in the IP1001_SPEC_CTRL_STATUS_2 register. It was also trying to set the IP1001_APS_ON bit , but never actually wrote back the register. The error checking was also incorrect in both this function and the reset function, so this patch fixes that up in a consistent fashion. Signed-off-by: David McKay <david.mckay@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-02-21 21:24:57 +00:00
net/phy: add IC+ IP101A and support APS. This patch adds the IC+ IP101A Single port 10/100 PHY and supports the APS (i.e. power saving mode while link is down) for both IP1001 and IP101A (where this mode is supported). Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-09-06 20:14:50 +00:00
netdev/phy/icplus: Correct broken phy_init code The code for ip1001_config_init() was totally broken if you were not using RGMII. Instead of returning an error code or zero it actually returned the value in the IP1001_SPEC_CTRL_STATUS_2 register. It was also trying to set the IP1001_APS_ON bit , but never actually wrote back the register. The error checking was also incorrect in both this function and the reset function, so this patch fixes that up in a consistent fashion. Signed-off-by: David McKay <david.mckay@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-02-21 21:24:57 +00:00
net/phy: add IC+ IP101A and support APS. This patch adds the IC+ IP101A Single port 10/100 PHY and supports the APS (i.e. power saving mode while link is down) for both IP1001 and IP101A (where this mode is supported). Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-09-06 20:14:50 +00:00
phy: add the IC+ IP1001 driver This patch adds the IC+ IP1001 (Gigabit Ethernet Transceiver) driver. I've had to add an additional delay (2ns) to adjust RX clock phase at GMII/ RGMII interface (according to the PHY data-sheet). This helps to have the RGMII working on some ST platforms. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2010-12-08 23:05:13 +00:00
net: phy: Utilize phy_interface_is_rgmii Update all open-coded tests for all 4 PHY_INTERFACE_MODE_RGMII* values to use the newly introduced helper: phy_interface_is_rgmii. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2015-05-26 12:19:59 -07:00
net: phy: icplus: Use the RGMII interface mode to configure clock delays Like several other PHY devices which support RGMII, the IC+1001 allows additional delays to by added to the RX_CLK and TX_CLK signals to compensate for skew between the clock and data signals. Previously this was always enabled, but this change makes use of the different RGMII interface modes to allow the user to specify whether this should be enabled. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2013-01-23 00:22:36 +00:00
net/phy: extra delay only for RGMII interfaces for IC+ IP 1001 The extra delay of 2ns to adjust RX clock phase is actually needed in RGMII mode. Tested on the HDK7108 (STx7108c2). Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-10-10 21:37:56 +00:00
netdev/phy/icplus: Correct broken phy_init code The code for ip1001_config_init() was totally broken if you were not using RGMII. Instead of returning an error code or zero it actually returned the value in the IP1001_SPEC_CTRL_STATUS_2 register. It was also trying to set the IP1001_APS_ON bit , but never actually wrote back the register. The error checking was also incorrect in both this function and the reset function, so this patch fixes that up in a consistent fashion. Signed-off-by: David McKay <david.mckay@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-02-21 21:24:57 +00:00
net: phy: icplus: Use the RGMII interface mode to configure clock delays Like several other PHY devices which support RGMII, the IC+1001 allows additional delays to by added to the RX_CLK and TX_CLK signals to compensate for skew between the clock and data signals. Previously this was always enabled, but this change makes use of the different RGMII interface modes to allow the user to specify whether this should be enabled. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2013-01-23 00:22:36 +00:00
net/phy: extra delay only for RGMII interfaces for IC+ IP 1001 The extra delay of 2ns to adjust RX clock phase is actually needed in RGMII mode. Tested on the HDK7108 (STx7108c2). Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-10-10 21:37:56 +00:00
netdev/phy/icplus: Correct broken phy_init code The code for ip1001_config_init() was totally broken if you were not using RGMII. Instead of returning an error code or zero it actually returned the value in the IP1001_SPEC_CTRL_STATUS_2 register. It was also trying to set the IP1001_APS_ON bit , but never actually wrote back the register. The error checking was also incorrect in both this function and the reset function, so this patch fixes that up in a consistent fashion. Signed-off-by: David McKay <david.mckay@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-02-21 21:24:57 +00:00
net/phy: extra delay only for RGMII interfaces for IC+ IP 1001 The extra delay of 2ns to adjust RX clock phase is actually needed in RGMII mode. Tested on the HDK7108 (STx7108c2). Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-10-10 21:37:56 +00:00
phy: add the IC+ IP1001 driver This patch adds the IC+ IP1001 (Gigabit Ethernet Transceiver) driver. I've had to add an additional delay (2ns) to adjust RX clock phase at GMII/ RGMII interface (according to the PHY data-sheet). This helps to have the RGMII working on some ST platforms. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2010-12-08 23:05:13 +00:00
netdev/phy/icplus: Correct broken phy_init code The code for ip1001_config_init() was totally broken if you were not using RGMII. Instead of returning an error code or zero it actually returned the value in the IP1001_SPEC_CTRL_STATUS_2 register. It was also trying to set the IP1001_APS_ON bit , but never actually wrote back the register. The error checking was also incorrect in both this function and the reset function, so this patch fixes that up in a consistent fashion. Signed-off-by: David McKay <david.mckay@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-02-21 21:24:57 +00:00
net/phy: add IC+ IP101A and support APS. This patch adds the IC+ IP101A Single port 10/100 PHY and supports the APS (i.e. power saving mode while link is down) for both IP1001 and IP101A (where this mode is supported). Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-09-06 20:14:50 +00:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
phy: Add an mdio_device structure Not all devices attached to an MDIO bus are phys. So add an mdio_device structure to represent the generic parts of an mdio device, and place this structure into the phy_device. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-01-06 20:11:16 +01:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
net: phy: rename PHY_IGNORE_INTERRUPT to PHY_MAC_INTERRUPT Some internal PHY's have their events like link change reported by the MAC interrupt. We have PHY_IGNORE_INTERRUPT to deal with this scenario. I'm not too happy with this name. We don't ignore interrupts, typically there is no interrupt exposed at a PHY level. So let's rename it to PHY_MAC_INTERRUPT. This is in line with phy_mac_interrupt(), which is called from the MAC interrupt handler to handle PHY events. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-14 15:16:23 +01:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
phy: Add an mdio_device structure Not all devices attached to an MDIO bus are phys. So add an mdio_device structure to represent the generic parts of an mdio device, and place this structure into the phy_device. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-01-06 20:11:16 +01:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
net: phy: icplus: allow configuring the interrupt function on IP101GR The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA Ethernet PHY. Due to it's limited amount of pins the RXER (receive error) and INTR32 (interrupt) functions share pin 21. By default the PHY is configured to output the "receive error" status on pin 21. Depending on the board layout and requirements we may want to re-configure the PHY to output the interrupt signal there. The mode of pin 21 can be configured in the "Digital I/O Specific Control Register" (register 29), bit 2: - 0 = RXER function - 1 = INTR(32) function Depending on the devicetree configuration we will now: - change the mode to either ther RXER or INTR32 function - keep the SEL_INTR32 value set by the bootloader (default) if no configuration is provided (to ensure that we're not breaking existing boards) - error out if conflicting configuration is given (RXER and INTR32 mode are enabled at the same time) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:59 +01:00
net: phy: icplus: don't set APS_EN bit on IP101G This bit is reserved as 'always-write-1'. While this is not a particular error, because we are only setting it, guard it by checking the model to prevent errors in the future. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:47 +01:00
net: phy: icplus: keep all ip101a_g functions together This simply moves ip101a_g_config_init right above ip101a_g_config_intr so all functions for the ICPlus IP101A/G PHYs are grouped together. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:55 +01:00
net: phy: icplus: allow configuring the interrupt function on IP101GR The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA Ethernet PHY. Due to it's limited amount of pins the RXER (receive error) and INTR32 (interrupt) functions share pin 21. By default the PHY is configured to output the "receive error" status on pin 21. Depending on the board layout and requirements we may want to re-configure the PHY to output the interrupt signal there. The mode of pin 21 can be configured in the "Digital I/O Specific Control Register" (register 29), bit 2: - 0 = RXER function - 1 = INTR(32) function Depending on the devicetree configuration we will now: - change the mode to either ther RXER or INTR32 function - keep the SEL_INTR32 value set by the bootloader (default) if no configuration is provided (to ensure that we're not breaking existing boards) - error out if conflicting configuration is given (RXER and INTR32 mode are enabled at the same time) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:59 +01:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: call phy_restore_page() when phy_select_page() fails The comments to phy_select_page() say that "phy_restore_page() must always be called after this, irrespective of success or failure of this call." If we don't call phy_restore_page() then we are still holding the phy_lock_mdio_bus() so it eventually leads to a dead lock. Fixes: 32ab60e53920 ("net: phy: icplus: add MDI/MDIX support for IP101A/G") Fixes: f9bc51e6cce2 ("net: phy: icplus: fix paged register access") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/YC+OpFGsDPXPnXM5@mwanda Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-02-19 13:10:44 +03:00
net: phy: icplus: keep all ip101a_g functions together This simply moves ip101a_g_config_init right above ip101a_g_config_intr so all functions for the ICPlus IP101A/G PHYs are grouped together. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:55 +01:00
net: phy: icplus: allow configuring the interrupt function on IP101GR The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA Ethernet PHY. Due to it's limited amount of pins the RXER (receive error) and INTR32 (interrupt) functions share pin 21. By default the PHY is configured to output the "receive error" status on pin 21. Depending on the board layout and requirements we may want to re-configure the PHY to output the interrupt signal there. The mode of pin 21 can be configured in the "Digital I/O Specific Control Register" (register 29), bit 2: - 0 = RXER function - 1 = INTR(32) function Depending on the devicetree configuration we will now: - change the mode to either ther RXER or INTR32 function - keep the SEL_INTR32 value set by the bootloader (default) if no configuration is provided (to ensure that we're not breaking existing boards) - error out if conflicting configuration is given (RXER and INTR32 mode are enabled at the same time) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:59 +01:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: allow configuring the interrupt function on IP101GR The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA Ethernet PHY. Due to it's limited amount of pins the RXER (receive error) and INTR32 (interrupt) functions share pin 21. By default the PHY is configured to output the "receive error" status on pin 21. Depending on the board layout and requirements we may want to re-configure the PHY to output the interrupt signal there. The mode of pin 21 can be configured in the "Digital I/O Specific Control Register" (register 29), bit 2: - 0 = RXER function - 1 = INTR(32) function Depending on the devicetree configuration we will now: - change the mode to either ther RXER or INTR32 function - keep the SEL_INTR32 value set by the bootloader (default) if no configuration is provided (to ensure that we're not breaking existing boards) - error out if conflicting configuration is given (RXER and INTR32 mode are enabled at the same time) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:59 +01:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: allow configuring the interrupt function on IP101GR The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA Ethernet PHY. Due to it's limited amount of pins the RXER (receive error) and INTR32 (interrupt) functions share pin 21. By default the PHY is configured to output the "receive error" status on pin 21. Depending on the board layout and requirements we may want to re-configure the PHY to output the interrupt signal there. The mode of pin 21 can be configured in the "Digital I/O Specific Control Register" (register 29), bit 2: - 0 = RXER function - 1 = INTR(32) function Depending on the devicetree configuration we will now: - change the mode to either ther RXER or INTR32 function - keep the SEL_INTR32 value set by the bootloader (default) if no configuration is provided (to ensure that we're not breaking existing boards) - error out if conflicting configuration is given (RXER and INTR32 mode are enabled at the same time) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:59 +01:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: allow configuring the interrupt function on IP101GR The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA Ethernet PHY. Due to it's limited amount of pins the RXER (receive error) and INTR32 (interrupt) functions share pin 21. By default the PHY is configured to output the "receive error" status on pin 21. Depending on the board layout and requirements we may want to re-configure the PHY to output the interrupt signal there. The mode of pin 21 can be configured in the "Digital I/O Specific Control Register" (register 29), bit 2: - 0 = RXER function - 1 = INTR(32) function Depending on the devicetree configuration we will now: - change the mode to either ther RXER or INTR32 function - keep the SEL_INTR32 value set by the bootloader (default) if no configuration is provided (to ensure that we're not breaking existing boards) - error out if conflicting configuration is given (RXER and INTR32 mode are enabled at the same time) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:59 +01:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: allow configuring the interrupt function on IP101GR The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA Ethernet PHY. Due to it's limited amount of pins the RXER (receive error) and INTR32 (interrupt) functions share pin 21. By default the PHY is configured to output the "receive error" status on pin 21. Depending on the board layout and requirements we may want to re-configure the PHY to output the interrupt signal there. The mode of pin 21 can be configured in the "Digital I/O Specific Control Register" (register 29), bit 2: - 0 = RXER function - 1 = INTR(32) function Depending on the devicetree configuration we will now: - change the mode to either ther RXER or INTR32 function - keep the SEL_INTR32 value set by the bootloader (default) if no configuration is provided (to ensure that we're not breaking existing boards) - error out if conflicting configuration is given (RXER and INTR32 mode are enabled at the same time) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:59 +01:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: don't set APS_EN bit on IP101G This bit is reserved as 'always-write-1'. While this is not a particular error, because we are only setting it, guard it by checking the model to prevent errors in the future. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:47 +01:00
net: phy: icplus: keep all ip101a_g functions together This simply moves ip101a_g_config_init right above ip101a_g_config_intr so all functions for the ICPlus IP101A/G PHYs are grouped together. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:55 +01:00
net: phy: icplus: don't set APS_EN bit on IP101G This bit is reserved as 'always-write-1'. While this is not a particular error, because we are only setting it, guard it by checking the model to prevent errors in the future. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:47 +01:00
net: phy: icplus: add PHY counter for IP101G The IP101G provides three counters: RX packets, CRC errors and symbol errors. The error counters can be configured to clear automatically on read. Unfortunately, this isn't true for the RX packet counter. Because of this and because the RX packet counter is more likely to overflow, than the error counters implement only support for the error counters. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:49 +01:00
net: phy: icplus: don't set APS_EN bit on IP101G This bit is reserved as 'always-write-1'. While this is not a particular error, because we are only setting it, guard it by checking the model to prevent errors in the future. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:47 +01:00
net: phy: icplus: keep all ip101a_g functions together This simply moves ip101a_g_config_init right above ip101a_g_config_intr so all functions for the ICPlus IP101A/G PHYs are grouped together. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:55 +01:00
net: phy: icplus: add MDI/MDIX support for IP101A/G Implement the operations to set desired mode and retrieve the current mode. This feature was tested with an IP101G. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:50 +01:00
net: phy: icplus: call phy_restore_page() when phy_select_page() fails The comments to phy_select_page() say that "phy_restore_page() must always be called after this, irrespective of success or failure of this call." If we don't call phy_restore_page() then we are still holding the phy_lock_mdio_bus() so it eventually leads to a dead lock. Fixes: 32ab60e53920 ("net: phy: icplus: add MDI/MDIX support for IP101A/G") Fixes: f9bc51e6cce2 ("net: phy: icplus: fix paged register access") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/YC+OpFGsDPXPnXM5@mwanda Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-02-19 13:10:44 +03:00
net: phy: icplus: add MDI/MDIX support for IP101A/G Implement the operations to set desired mode and retrieve the current mode. This feature was tested with an IP101G. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:50 +01:00
net: phy: icplus: call phy_restore_page() when phy_select_page() fails The comments to phy_select_page() say that "phy_restore_page() must always be called after this, irrespective of success or failure of this call." If we don't call phy_restore_page() then we are still holding the phy_lock_mdio_bus() so it eventually leads to a dead lock. Fixes: 32ab60e53920 ("net: phy: icplus: add MDI/MDIX support for IP101A/G") Fixes: f9bc51e6cce2 ("net: phy: icplus: fix paged register access") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/YC+OpFGsDPXPnXM5@mwanda Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-02-19 13:10:44 +03:00
net: phy: icplus: add MDI/MDIX support for IP101A/G Implement the operations to set desired mode and retrieve the current mode. This feature was tested with an IP101G. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:50 +01:00
net: phy: icplus: call phy_restore_page() when phy_select_page() fails The comments to phy_select_page() say that "phy_restore_page() must always be called after this, irrespective of success or failure of this call." If we don't call phy_restore_page() then we are still holding the phy_lock_mdio_bus() so it eventually leads to a dead lock. Fixes: 32ab60e53920 ("net: phy: icplus: add MDI/MDIX support for IP101A/G") Fixes: f9bc51e6cce2 ("net: phy: icplus: fix paged register access") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/YC+OpFGsDPXPnXM5@mwanda Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-02-19 13:10:44 +03:00
net: phy: icplus: add MDI/MDIX support for IP101A/G Implement the operations to set desired mode and retrieve the current mode. This feature was tested with an IP101G. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:50 +01:00
net: phy: icplus: remove the use .ack_interrupt() In preparation of removing the .ack_interrupt() callback, we must replace its occurrences (aka phy_clear_interrupt), from the 2 places where it is called from (phy_enable_interrupts and phy_disable_interrupts), with equivalent functionality. This means that clearing interrupts now becomes something that the PHY driver is responsible of doing, before enabling interrupts and after clearing them. Make this driver follow the new contract. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-23 17:38:06 +02:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: remove the use .ack_interrupt() In preparation of removing the .ack_interrupt() callback, we must replace its occurrences (aka phy_clear_interrupt), from the 2 places where it is called from (phy_enable_interrupts and phy_disable_interrupts), with equivalent functionality. This means that clearing interrupts now becomes something that the PHY driver is responsible of doing, before enabling interrupts and after clearing them. Make this driver follow the new contract. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-23 17:38:06 +02:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: remove the use .ack_interrupt() In preparation of removing the .ack_interrupt() callback, we must replace its occurrences (aka phy_clear_interrupt), from the 2 places where it is called from (phy_enable_interrupts and phy_disable_interrupts), with equivalent functionality. This means that clearing interrupts now becomes something that the PHY driver is responsible of doing, before enabling interrupts and after clearing them. Make this driver follow the new contract. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-23 17:38:06 +02:00
net: phy: icplus: add config_intr callback Move IRQ configuration for IP101A/G from config_init to config_intr callback. Reasons: 1. This allows phylib to disable interrupts if needed. 2. Icplus was the only driver supporting interrupts w/o defining a config_intr callback. Now we can add a phylib plausibility check disabling interrupt mode if one of the two irq-related callbacks isn't defined. I don't own hardware with this PHY, and the change is based on the datasheet for IP101A LF (which is supposed to be register-compatible with IP101A/G). Change is compile-tested only. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-11 21:49:12 +01:00
net: phy: icplus: remove the use .ack_interrupt() In preparation of removing the .ack_interrupt() callback, we must replace its occurrences (aka phy_clear_interrupt), from the 2 places where it is called from (phy_enable_interrupts and phy_disable_interrupts), with equivalent functionality. This means that clearing interrupts now becomes something that the PHY driver is responsible of doing, before enabling interrupts and after clearing them. Make this driver follow the new contract. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-23 17:38:06 +02:00
net: phy: icplus: add config_intr callback Move IRQ configuration for IP101A/G from config_init to config_intr callback. Reasons: 1. This allows phylib to disable interrupts if needed. 2. Icplus was the only driver supporting interrupts w/o defining a config_intr callback. Now we can add a phylib plausibility check disabling interrupt mode if one of the two irq-related callbacks isn't defined. I don't own hardware with this PHY, and the change is based on the datasheet for IP101A LF (which is supposed to be register-compatible with IP101A/G). Change is compile-tested only. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-11 21:49:12 +01:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: remove the use .ack_interrupt() In preparation of removing the .ack_interrupt() callback, we must replace its occurrences (aka phy_clear_interrupt), from the 2 places where it is called from (phy_enable_interrupts and phy_disable_interrupts), with equivalent functionality. This means that clearing interrupts now becomes something that the PHY driver is responsible of doing, before enabling interrupts and after clearing them. Make this driver follow the new contract. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-23 17:38:06 +02:00
net: phy: icplus: rename IP101A_G_NO_IRQ to IP101A_G_IRQ_ALL_MASK The datasheet uses the name "All Mask" for this bit. Change the name of our #define to be consistent with the datasheet. While here also replace the tab between the #define and IP101A_G_IRQ_ALL_MASK with a space. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:57 +01:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: remove the use .ack_interrupt() In preparation of removing the .ack_interrupt() callback, we must replace its occurrences (aka phy_clear_interrupt), from the 2 places where it is called from (phy_enable_interrupts and phy_disable_interrupts), with equivalent functionality. This means that clearing interrupts now becomes something that the PHY driver is responsible of doing, before enabling interrupts and after clearing them. Make this driver follow the new contract. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-23 17:38:06 +02:00
net: phy: icplus: add config_intr callback Move IRQ configuration for IP101A/G from config_init to config_intr callback. Reasons: 1. This allows phylib to disable interrupts if needed. 2. Icplus was the only driver supporting interrupts w/o defining a config_intr callback. Now we can add a phylib plausibility check disabling interrupt mode if one of the two irq-related callbacks isn't defined. I don't own hardware with this PHY, and the change is based on the datasheet for IP101A LF (which is supposed to be register-compatible with IP101A/G). Change is compile-tested only. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-11 21:49:12 +01:00
net: phy: icplus: remove the use .ack_interrupt() In preparation of removing the .ack_interrupt() callback, we must replace its occurrences (aka phy_clear_interrupt), from the 2 places where it is called from (phy_enable_interrupts and phy_disable_interrupts), with equivalent functionality. This means that clearing interrupts now becomes something that the PHY driver is responsible of doing, before enabling interrupts and after clearing them. Make this driver follow the new contract. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-23 17:38:06 +02:00
net: phy: icplus: add config_intr callback Move IRQ configuration for IP101A/G from config_init to config_intr callback. Reasons: 1. This allows phylib to disable interrupts if needed. 2. Icplus was the only driver supporting interrupts w/o defining a config_intr callback. Now we can add a phylib plausibility check disabling interrupt mode if one of the two irq-related callbacks isn't defined. I don't own hardware with this PHY, and the change is based on the datasheet for IP101A LF (which is supposed to be register-compatible with IP101A/G). Change is compile-tested only. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-11 21:49:12 +01:00
net: phy: icplus: implement generic .handle_interrupt() callback In an attempt to actually support shared IRQs in phylib, we now move the responsibility of triggering the phylib state machine or just returning IRQ_NONE, based on the IRQ status register, to the PHY driver. Having 3 different IRQ handling callbacks (.handle_interrupt(), .did_interrupt() and .ack_interrupt() ) is confusing so let the PHY driver implement directly an IRQ handler like any other device driver. Make this driver follow the new convention. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-23 17:38:05 +02:00
net: phy: icplus: implement .did_interrupt for IP101A/G The IP101A_G_IRQ_CONF_STATUS register has bits to detect which interrupts have fired. Implement the .did_interrupt callback to let the PHY core know whether the interrupt was for this specific PHY. This is useful for debugging interrupt problems with 32-pin IP101GR PHYs where the interrupt line is shared with the RX_ERR (receive error status) signal. The default values are: - RX_ERR is enabled by default (LOW means that there is no receive error) - the PHY's interrupt line is configured "active low" by default Without any additional changes there is a flood of interrupts if the RX_ERR/INTR32 signal is configured in RX_ERR mode (which is the default). Having a did_interrupt ensures that the PHY core returns IRQ_NONE instead of endlessly triggering the PHY state machine. Additionally the kernel will report this after a while: irq 28: nobody cared (try booting with the "irqpoll" option) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:58 +01:00
net: phy: icplus: implement generic .handle_interrupt() callback In an attempt to actually support shared IRQs in phylib, we now move the responsibility of triggering the phylib state machine or just returning IRQ_NONE, based on the IRQ status register, to the PHY driver. Having 3 different IRQ handling callbacks (.handle_interrupt(), .did_interrupt() and .ack_interrupt() ) is confusing so let the PHY driver implement directly an IRQ handler like any other device driver. Make this driver follow the new convention. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-23 17:38:05 +02:00
net: phy: icplus: implement .did_interrupt for IP101A/G The IP101A_G_IRQ_CONF_STATUS register has bits to detect which interrupts have fired. Implement the .did_interrupt callback to let the PHY core know whether the interrupt was for this specific PHY. This is useful for debugging interrupt problems with 32-pin IP101GR PHYs where the interrupt line is shared with the RX_ERR (receive error status) signal. The default values are: - RX_ERR is enabled by default (LOW means that there is no receive error) - the PHY's interrupt line is configured "active low" by default Without any additional changes there is a flood of interrupts if the RX_ERR/INTR32 signal is configured in RX_ERR mode (which is the default). Having a did_interrupt ensures that the PHY core returns IRQ_NONE instead of endlessly triggering the PHY state machine. Additionally the kernel will report this after a while: irq 28: nobody cared (try booting with the "irqpoll" option) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:58 +01:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: implement generic .handle_interrupt() callback In an attempt to actually support shared IRQs in phylib, we now move the responsibility of triggering the phylib state machine or just returning IRQ_NONE, based on the IRQ status register, to the PHY driver. Having 3 different IRQ handling callbacks (.handle_interrupt(), .did_interrupt() and .ack_interrupt() ) is confusing so let the PHY driver implement directly an IRQ handler like any other device driver. Make this driver follow the new convention. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-23 17:38:05 +02:00
net: phy: icplus: implement .did_interrupt for IP101A/G The IP101A_G_IRQ_CONF_STATUS register has bits to detect which interrupts have fired. Implement the .did_interrupt callback to let the PHY core know whether the interrupt was for this specific PHY. This is useful for debugging interrupt problems with 32-pin IP101GR PHYs where the interrupt line is shared with the RX_ERR (receive error status) signal. The default values are: - RX_ERR is enabled by default (LOW means that there is no receive error) - the PHY's interrupt line is configured "active low" by default Without any additional changes there is a flood of interrupts if the RX_ERR/INTR32 signal is configured in RX_ERR mode (which is the default). Having a did_interrupt ensures that the PHY core returns IRQ_NONE instead of endlessly triggering the PHY state machine. Additionally the kernel will report this after a while: irq 28: nobody cared (try booting with the "irqpoll" option) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:58 +01:00
net: phy: icplus: implement generic .handle_interrupt() callback In an attempt to actually support shared IRQs in phylib, we now move the responsibility of triggering the phylib state machine or just returning IRQ_NONE, based on the IRQ status register, to the PHY driver. Having 3 different IRQ handling callbacks (.handle_interrupt(), .did_interrupt() and .ack_interrupt() ) is confusing so let the PHY driver implement directly an IRQ handler like any other device driver. Make this driver follow the new convention. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-23 17:38:05 +02:00
net: phy: icplus: implement .did_interrupt for IP101A/G The IP101A_G_IRQ_CONF_STATUS register has bits to detect which interrupts have fired. Implement the .did_interrupt callback to let the PHY core know whether the interrupt was for this specific PHY. This is useful for debugging interrupt problems with 32-pin IP101GR PHYs where the interrupt line is shared with the RX_ERR (receive error status) signal. The default values are: - RX_ERR is enabled by default (LOW means that there is no receive error) - the PHY's interrupt line is configured "active low" by default Without any additional changes there is a flood of interrupts if the RX_ERR/INTR32 signal is configured in RX_ERR mode (which is the default). Having a did_interrupt ensures that the PHY core returns IRQ_NONE instead of endlessly triggering the PHY state machine. Additionally the kernel will report this after a while: irq 28: nobody cared (try booting with the "irqpoll" option) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:58 +01:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: split IP101A/G driver Unfortunately, the IP101A and IP101G share the same PHY identifier. While most of the functions are somewhat backwards compatible, there is for example the APS_EN bit on the IP101A but on the IP101G this bit reserved. Also, the IP101G has many more functionalities. Deduce the model by accessing the page select register which - according to the datasheet - is not available on the IP101A. If this register is writable, assume we have an IP101G. Split the combined IP101A/G driver into two separate drivers. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:46 +01:00
net: phy: pass PHY driver to .match_phy_device OP Pass PHY driver pointer to .match_phy_device OP in addition to phydev. Having access to the PHY driver struct might be useful to check the PHY ID of the driver is being matched for in case the PHY ID scanned in the phydev is not consistent. A scenario for this is a PHY that change PHY ID after a firmware is loaded, in such case, the PHY ID stored in PHY device struct is not valid anymore and PHY will manually scan the ID in the match_phy_device function. Having the PHY driver info is also useful for those PHY driver that implement multiple simple .match_phy_device OP to match specific MMD PHY ID. With this extra info if the parsing logic is the same, the matching function can be generalized by using the phy_id in the PHY driver instead of hardcoding. Rust wrapper callback is updated to align to the new match_phy_device arguments. Suggested-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Benno Lossin <lossin@kernel.org> # for Rust Reviewed-by: FUJITA Tomonori <fujita.tomonori@gmail.com> Link: https://patch.msgid.link/20250517201353.5137-2-ansuelsmth@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-05-17 22:13:45 +02:00
net: phy: icplus: split IP101A/G driver Unfortunately, the IP101A and IP101G share the same PHY identifier. While most of the functions are somewhat backwards compatible, there is for example the APS_EN bit on the IP101A but on the IP101G this bit reserved. Also, the IP101G has many more functionalities. Deduce the model by accessing the page select register which - according to the datasheet - is not available on the IP101A. If this register is writable, assume we have an IP101G. Split the combined IP101A/G driver into two separate drivers. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:46 +01:00
net: phy: pass PHY driver to .match_phy_device OP Pass PHY driver pointer to .match_phy_device OP in addition to phydev. Having access to the PHY driver struct might be useful to check the PHY ID of the driver is being matched for in case the PHY ID scanned in the phydev is not consistent. A scenario for this is a PHY that change PHY ID after a firmware is loaded, in such case, the PHY ID stored in PHY device struct is not valid anymore and PHY will manually scan the ID in the match_phy_device function. Having the PHY driver info is also useful for those PHY driver that implement multiple simple .match_phy_device OP to match specific MMD PHY ID. With this extra info if the parsing logic is the same, the matching function can be generalized by using the phy_id in the PHY driver instead of hardcoding. Rust wrapper callback is updated to align to the new match_phy_device arguments. Suggested-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Benno Lossin <lossin@kernel.org> # for Rust Reviewed-by: FUJITA Tomonori <fujita.tomonori@gmail.com> Link: https://patch.msgid.link/20250517201353.5137-2-ansuelsmth@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-05-17 22:13:45 +02:00
net: phy: icplus: split IP101A/G driver Unfortunately, the IP101A and IP101G share the same PHY identifier. While most of the functions are somewhat backwards compatible, there is for example the APS_EN bit on the IP101A but on the IP101G this bit reserved. Also, the IP101G has many more functionalities. Deduce the model by accessing the page select register which - according to the datasheet - is not available on the IP101A. If this register is writable, assume we have an IP101G. Split the combined IP101A/G driver into two separate drivers. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:46 +01:00
net: phy: icplus: add PHY counter for IP101G The IP101G provides three counters: RX packets, CRC errors and symbol errors. The error counters can be configured to clear automatically on read. Unfortunately, this isn't true for the RX packet counter. Because of this and because the RX packet counter is more likely to overflow, than the error counters implement only support for the error counters. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:49 +01:00
net: phy: use ethtool string helpers These are the preferred way to copy ethtool strings. Avoids incrementing pointers all over the place. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://patch.msgid.link/20241029234641.11448-1-rosenp@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-29 16:46:41 -07:00
net: phy: icplus: add PHY counter for IP101G The IP101G provides three counters: RX packets, CRC errors and symbol errors. The error counters can be configured to clear automatically on read. Unfortunately, this isn't true for the RX packet counter. Because of this and because the RX packet counter is more likely to overflow, than the error counters implement only support for the error counters. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:49 +01:00
phylib: Support registering a bunch of drivers If registering of one of them fails, all already registered drivers of this module will be unregistered. Use the new register/unregister functions in all drivers registering more than one driver. amd.c, realtek.c: Simplify: directly return registration result. Tested with broadcom.c All others compile-tested. Signed-off-by: Christian Hohnstaedt <chohnstaedt@innominate.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-07-04 05:44:34 +00:00
net: phy: icplus: use PHY_ID_MATCH_MODEL() macro Simpify the initializations of the structures. There is no functional change. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:42 +01:00
phylib: add the ICPlus IP175C PHY driver The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition to a dedicated 100Mbit/s WAN port. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-05-11 18:24:51 -05:00
net: phy: switch drivers to use dynamic feature detection Recently genphy_read_abilities() has been added that dynamically detects clause 22 PHY abilities. I *think* this detection should work with all supported PHY's, at least for the ones with basic features sets, i.e. PHY_BASIC_FEATURES and PHY_GBIT_FEATURES. So let's remove setting these features explicitly and rely on phylib feature detection. I don't have access to most of these PHY's, therefore I'd appreciate regression testing. v2: - make the feature constant a comment so that readers know which features are supported by the respective PHY Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-12 20:47:03 +02:00
net: phy: icplus: drop address operator for functions Don't sometimes use the address operator and sometimes not. Drop it and make the code look uniform. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:44 +01:00
phy: add suspend/resume in the ic+ Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2010-07-20 13:24:25 -07:00
phylib: Support registering a bunch of drivers If registering of one of them fails, all already registered drivers of this module will be unregistered. Use the new register/unregister functions in all drivers registering more than one driver. amd.c, realtek.c: Simplify: directly return registration result. Tested with broadcom.c All others compile-tested. Signed-off-by: Christian Hohnstaedt <chohnstaedt@innominate.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-07-04 05:44:34 +00:00
net: phy: icplus: use PHY_ID_MATCH_MODEL() macro Simpify the initializations of the structures. There is no functional change. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:42 +01:00
phy: add the IC+ IP1001 driver This patch adds the IC+ IP1001 (Gigabit Ethernet Transceiver) driver. I've had to add an additional delay (2ns) to adjust RX clock phase at GMII/ RGMII interface (according to the PHY data-sheet). This helps to have the RGMII working on some ST platforms. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2010-12-08 23:05:13 +00:00
net: phy: switch drivers to use dynamic feature detection Recently genphy_read_abilities() has been added that dynamically detects clause 22 PHY abilities. I *think* this detection should work with all supported PHY's, at least for the ones with basic features sets, i.e. PHY_BASIC_FEATURES and PHY_GBIT_FEATURES. So let's remove setting these features explicitly and rely on phylib feature detection. I don't have access to most of these PHY's, therefore I'd appreciate regression testing. v2: - make the feature constant a comment so that readers know which features are supported by the respective PHY Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-12 20:47:03 +02:00
net: phy: icplus: drop address operator for functions Don't sometimes use the address operator and sometimes not. Drop it and make the code look uniform. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:44 +01:00
net: phy: icplus: use the .soft_reset() of the phy-core The PHY core already resets the PHY before .config_init() if a .soft_reset() op is registered. Drop the open-coded ip1xx_reset(). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:45 +01:00
phy: add the IC+ IP1001 driver This patch adds the IC+ IP1001 (Gigabit Ethernet Transceiver) driver. I've had to add an additional delay (2ns) to adjust RX clock phase at GMII/ RGMII interface (according to the PHY data-sheet). This helps to have the RGMII working on some ST platforms. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2010-12-08 23:05:13 +00:00
phylib: Support registering a bunch of drivers If registering of one of them fails, all already registered drivers of this module will be unregistered. Use the new register/unregister functions in all drivers registering more than one driver. amd.c, realtek.c: Simplify: directly return registration result. Tested with broadcom.c All others compile-tested. Signed-off-by: Christian Hohnstaedt <chohnstaedt@innominate.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-07-04 05:44:34 +00:00
net: phy: icplus: split IP101A/G driver Unfortunately, the IP101A and IP101G share the same PHY identifier. While most of the functions are somewhat backwards compatible, there is for example the APS_EN bit on the IP101A but on the IP101G this bit reserved. Also, the IP101G has many more functionalities. Deduce the model by accessing the page select register which - according to the datasheet - is not available on the IP101A. If this register is writable, assume we have an IP101G. Split the combined IP101A/G driver into two separate drivers. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:46 +01:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: split IP101A/G driver Unfortunately, the IP101A and IP101G share the same PHY identifier. While most of the functions are somewhat backwards compatible, there is for example the APS_EN bit on the IP101A but on the IP101G this bit reserved. Also, the IP101G has many more functionalities. Deduce the model by accessing the page select register which - according to the datasheet - is not available on the IP101A. If this register is writable, assume we have an IP101G. Split the combined IP101A/G driver into two separate drivers. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:46 +01:00
net: phy: icplus: don't set APS_EN bit on IP101G This bit is reserved as 'always-write-1'. While this is not a particular error, because we are only setting it, guard it by checking the model to prevent errors in the future. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:47 +01:00
net: phy: icplus: add MDI/MDIX support for IP101A/G Implement the operations to set desired mode and retrieve the current mode. This feature was tested with an IP101G. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:50 +01:00
net: phy: icplus: split IP101A/G driver Unfortunately, the IP101A and IP101G share the same PHY identifier. While most of the functions are somewhat backwards compatible, there is for example the APS_EN bit on the IP101A but on the IP101G this bit reserved. Also, the IP101G has many more functionalities. Deduce the model by accessing the page select register which - according to the datasheet - is not available on the IP101A. If this register is writable, assume we have an IP101G. Split the combined IP101A/G driver into two separate drivers. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:46 +01:00
net: phy: icplus: allow configuring the interrupt function on IP101GR The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA Ethernet PHY. Due to it's limited amount of pins the RXER (receive error) and INTR32 (interrupt) functions share pin 21. By default the PHY is configured to output the "receive error" status on pin 21. Depending on the board layout and requirements we may want to re-configure the PHY to output the interrupt signal there. The mode of pin 21 can be configured in the "Digital I/O Specific Control Register" (register 29), bit 2: - 0 = RXER function - 1 = INTR(32) function Depending on the devicetree configuration we will now: - change the mode to either ther RXER or INTR32 function - keep the SEL_INTR32 value set by the bootloader (default) if no configuration is provided (to ensure that we're not breaking existing boards) - error out if conflicting configuration is given (RXER and INTR32 mode are enabled at the same time) Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-18 22:23:59 +01:00
net: phy: icplus: fix paged register access Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:48 +01:00
net: phy: icplus: add config_intr callback Move IRQ configuration for IP101A/G from config_init to config_intr callback. Reasons: 1. This allows phylib to disable interrupts if needed. 2. Icplus was the only driver supporting interrupts w/o defining a config_intr callback. Now we can add a phylib plausibility check disabling interrupt mode if one of the two irq-related callbacks isn't defined. I don't own hardware with this PHY, and the change is based on the datasheet for IP101A LF (which is supposed to be register-compatible with IP101A/G). Change is compile-tested only. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-11 21:49:12 +01:00
net: phy: icplus: implement generic .handle_interrupt() callback In an attempt to actually support shared IRQs in phylib, we now move the responsibility of triggering the phylib state machine or just returning IRQ_NONE, based on the IRQ status register, to the PHY driver. Having 3 different IRQ handling callbacks (.handle_interrupt(), .did_interrupt() and .ack_interrupt() ) is confusing so let the PHY driver implement directly an IRQ handler like any other device driver. Make this driver follow the new convention. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-23 17:38:05 +02:00
net: phy: icplus: don't set APS_EN bit on IP101G This bit is reserved as 'always-write-1'. While this is not a particular error, because we are only setting it, guard it by checking the model to prevent errors in the future. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:47 +01:00
net: phy: icplus: add MDI/MDIX support for IP101A/G Implement the operations to set desired mode and retrieve the current mode. This feature was tested with an IP101G. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:50 +01:00
net: phy: icplus: use the .soft_reset() of the phy-core The PHY core already resets the PHY before .config_init() if a .soft_reset() op is registered. Drop the open-coded ip1xx_reset(). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:45 +01:00
net: phy: icplus: add PHY counter for IP101G The IP101G provides three counters: RX packets, CRC errors and symbol errors. The error counters can be configured to clear automatically on read. Unfortunately, this isn't true for the RX packet counter. Because of this and because the RX packet counter is more likely to overflow, than the error counters implement only support for the error counters. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:49 +01:00
net/phy: add IC+ IP101A and support APS. This patch adds the IC+ IP101A Single port 10/100 PHY and supports the APS (i.e. power saving mode while link is down) for both IP1001 and IP101A (where this mode is supported). Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-09-06 20:14:50 +00:00
phylib: Support registering a bunch of drivers If registering of one of them fails, all already registered drivers of this module will be unregistered. Use the new register/unregister functions in all drivers registering more than one driver. amd.c, realtek.c: Simplify: directly return registration result. Tested with broadcom.c All others compile-tested. Signed-off-by: Christian Hohnstaedt <chohnstaedt@innominate.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-07-04 05:44:34 +00:00
net/phy: add IC+ IP101A and support APS. This patch adds the IC+ IP101A Single port 10/100 PHY and supports the APS (i.e. power saving mode while link is down) for both IP1001 and IP101A (where this mode is supported). Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-09-06 20:14:50 +00:00
net: phy: replace phy_drivers_register calls Replace module init/exit which only calls phy_drivers_register with module_phy_driver macro. Tested using Micrel driver, and otherwise compile-tested only. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-11-11 19:45:59 +01:00
phylib: Add module table to all existing phy drivers Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2010-04-02 01:05:56 +00:00
net: phy: Constify struct mdio_device_id 'struct mdio_device_id' is not modified in these drivers. Constifying these structures moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig, as an example: Before: ====== text data bss dec hex filename 27014 12792 0 39806 9b7e drivers/net/phy/broadcom.o After: ===== text data bss dec hex filename 27206 12600 0 39806 9b7e drivers/net/phy/broadcom.o Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/403c381b7d9156b67ad68ffc44b8eee70c5e86a9.1736691226.git.christophe.jaillet@wanadoo.fr Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-01-12 15:14:50 +01:00
net: phy: icplus: use PHY_ID_MATCH_MODEL() macro Simpify the initializations of the structures. There is no functional change. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:42 +01:00
net: phy: icplus: use PHY_ID_MATCH_EXACT() for IP101A/G According to the datasheet of the IP101A/G there is no revision field and MII_PHYSID2 always reads as 0x0c54. Use PHY_ID_MATCH_EXACT() then. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11 08:47:43 +01:00
phylib: Add module table to all existing phy drivers Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2010-04-02 01:05:56 +00:00