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linux/include/soc/tegra/fuse.h

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-28 10:10:04 -07:00
ARM: tegra: add function to read chipid Add function to read chip id from APB MISC registers. This function will also get called from clock driver to flush write operations on apb bus. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 13:16:19 +05:30
soc/tegra: fuse: Add support for Tegra264 Add support for Tegra264 to the fuse handling code. Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-05-11 16:20:48 +03:00
ARM: tegra: add function to read chipid Add function to read chip id from APB MISC registers. This function will also get called from clock driver to flush write operations on apb bus. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 13:16:19 +05:30
ARM: tegra: Move includes to include/soc/tegra In order to not clutter the include/linux directory with SoC specific headers, move the Tegra-specific headers out into a separate directory. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17 13:17:24 +02:00
ARM: tegra: add function to read chipid Add function to read chip id from APB MISC registers. This function will also get called from clock driver to flush write operations on apb bus. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 13:16:19 +05:30
soc/tegra: fuse: Add stubs needed for compile testing Add stubs needed for compile-testing of tegra-cpuidle driver. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-09-12 23:29:02 +03:00
ARM: tegra: Use a function to get the chip ID Instead of using a simple variable access to get at the Tegra chip ID, use a function so that we can run additional code. This can be used to determine where the chip ID is being accessed without being available. That in turn will be handy for resolving boot sequence dependencies in order to convert more code to regular initcalls rather than a sequence fixed by Tegra SoC setup code. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-11 09:52:41 +02:00
soc/tegra: Add Tegra132 support Add the chip ID for the NVIDIA Tegra132 SoC family. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-08 08:24:45 +01:00
soc/tegra: fuse: Add Tegra210 support Add Tegra210 support to the fuses driver and add Tegra210-specific speedo definitions. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-29 16:55:57 +02:00
soc/tegra: fuse: Add Tegra186 and Tegra194 SoC IDs SoC IDs for these generations had never been defined. Do so now. Signed-off-by: Sandipan Patra <spatra@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-26 10:44:01 +02:00
soc/tegra: fuse: Add Tegra234 support Add support for FUSE block found on the Tegra234 SoC, which is largely similar to the IP found on previous generations. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-17 12:07:47 +02:00
soc/tegra: fuse: Add support for Tegra241 Add support for Tegra241 which use ACPI boot. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-10-17 10:53:22 +05:30
soc/tegra: fuse: Add support for Tegra264 Add support for Tegra264 to the fuse handling code. Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-05-11 16:20:48 +03:00
ARM: tegra: Use a function to get the chip ID Instead of using a simple variable access to get at the Tegra chip ID, use a function so that we can run additional code. This can be used to determine where the chip ID is being accessed without being available. That in turn will be handy for resolving boot sequence dependencies in order to convert more code to regular initcalls rather than a sequence fixed by Tegra SoC setup code. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-11 09:52:41 +02:00
soc/tegra: Add efuse driver for Tegra Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This replaces functionality previously provided in arch/arm/mach-tegra, which is removed in this patch. While at it, move the only user of the global tegra_revision variable over to tegra_sku_info.revision and export tegra_fuse_readl() to allow drivers to read calibration fuses. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-12 18:36:37 +03:00
phy: tegra: Add Tegra210 support Add support for the XUSB pad controller found on Tegra210 SoCs. The hardware is roughly the same, but some of the registers have been moved around and the number and type of supported pads has changed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:25:02 +01:00
soc/tegra: Add efuse driver for Tegra Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This replaces functionality previously provided in arch/arm/mach-tegra, which is removed in this patch. While at it, move the only user of the global tegra_revision variable over to tegra_sku_info.revision and export tegra_fuse_readl() to allow drivers to read calibration fuses. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-12 18:36:37 +03:00
ARM: tegra: Use a function to get the chip ID Instead of using a simple variable access to get at the Tegra chip ID, use a function so that we can run additional code. This can be used to determine where the chip ID is being accessed without being available. That in turn will be handy for resolving boot sequence dependencies in order to convert more code to regular initcalls rather than a sequence fixed by Tegra SoC setup code. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-11 09:52:41 +02:00
ARM: tegra: move fuse exports to soc/tegra/fuse.h All fuse related functionality will move to a driver in the following patches. To prepare for this, export all the required functionality in a global header file and move all users of fuse.h to soc/tegra/fuse.h. While we're at it, remove tegra_bct_strapping, as its only user was removed in Commit a7cbe92cef27 ("ARM: tegra: remove tegra EMC scaling driver"). Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-12 18:36:36 +03:00
soc/tegra: fuse: Use platform info with SoC revision Tegra pre-silicon platforms do not have chip revisions. This makes the revision SoC attribute meaningless on these platforms. Instead, populate the revision SoC attribute with a combination of the platform name and the chip revision for silicon platforms, and simply with the platform name on pre-silicon platforms. Signed-off-by: Kartik <kkartik@nvidia.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-09 19:50:22 +05:30
soc/tegra: Add efuse driver for Tegra Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This replaces functionality previously provided in arch/arm/mach-tegra, which is removed in this patch. While at it, move the only user of the global tegra_revision variable over to tegra_sku_info.revision and export tegra_fuse_readl() to allow drivers to read calibration fuses. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-12 18:36:37 +03:00
soc/tegra: fuse: Rename core_* to soc_* There's a mixture of core_* and soc_* prefixes for variables storing information related to the VDD_CORE rail. Choose one (soc_*) and use it more consistently. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-23 14:44:08 +01:00
soc/tegra: Add efuse driver for Tegra Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This replaces functionality previously provided in arch/arm/mach-tegra, which is removed in this patch. While at it, move the only user of the global tegra_revision variable over to tegra_sku_info.revision and export tegra_fuse_readl() to allow drivers to read calibration fuses. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-12 18:36:37 +03:00
soc/tegra: fuse: Add Tegra210 support Add Tegra210 support to the fuses driver and add Tegra210-specific speedo definitions. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-29 16:55:57 +02:00
soc/tegra: Add efuse driver for Tegra Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This replaces functionality previously provided in arch/arm/mach-tegra, which is removed in this patch. While at it, move the only user of the global tegra_revision variable over to tegra_sku_info.revision and export tegra_fuse_readl() to allow drivers to read calibration fuses. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-12 18:36:37 +03:00
soc/tegra: fuse: Add Tegra210 support Add Tegra210 support to the fuses driver and add Tegra210-specific speedo definitions. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-29 16:55:57 +02:00
soc/tegra: Add efuse driver for Tegra Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This replaces functionality previously provided in arch/arm/mach-tegra, which is removed in this patch. While at it, move the only user of the global tegra_revision variable over to tegra_sku_info.revision and export tegra_fuse_readl() to allow drivers to read calibration fuses. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-12 18:36:37 +03:00
soc/tegra: fuse: Use platform info with SoC revision Tegra pre-silicon platforms do not have chip revisions. This makes the revision SoC attribute meaningless on these platforms. Instead, populate the revision SoC attribute with a combination of the platform name and the chip revision for silicon platforms, and simply with the platform name on pre-silicon platforms. Signed-off-by: Kartik <kkartik@nvidia.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-09 19:50:22 +05:30
soc/tegra: Add efuse driver for Tegra Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This replaces functionality previously provided in arch/arm/mach-tegra, which is removed in this patch. While at it, move the only user of the global tegra_revision variable over to tegra_sku_info.revision and export tegra_fuse_readl() to allow drivers to read calibration fuses. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-12 18:36:37 +03:00
soc/tegra: fuse: Add stubs needed for compile-testing Add missing stubs that will allow Tegra memory driver to be compile-tested by kernel build bots. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-28 02:54:04 +03:00
ARM: tegra: move fuse exports to soc/tegra/fuse.h All fuse related functionality will move to a driver in the following patches. To prepare for this, export all the required functionality in a global header file and move all users of fuse.h to soc/tegra/fuse.h. While we're at it, remove tegra_bct_strapping, as its only user was removed in Commit a7cbe92cef27 ("ARM: tegra: remove tegra EMC scaling driver"). Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-12 18:36:36 +03:00
soc/tegra: fuse: Add RAM code reader helper Needed for the EMC and MC drivers to know what timings from the DT to use. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-03-12 15:47:55 +01:00
soc/tegra: Add efuse driver for Tegra Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This replaces functionality previously provided in arch/arm/mach-tegra, which is removed in this patch. While at it, move the only user of the global tegra_revision variable over to tegra_sku_info.revision and export tegra_fuse_readl() to allow drivers to read calibration fuses. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-12 18:36:37 +03:00
soc/tegra: fuse: Add stubs needed for compile testing Add stubs needed for compile-testing of tegra-cpuidle driver. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-09-12 23:29:02 +03:00
soc/tegra: Set ERD bit to mask inband errors Add a function to set the ERD (Error Response Disable) bit in the MISCREG_CCROC_ERR_CONFIG register from the Control Backbone (CBB) error handler driver. ERD bit allows masking of SError due to inband errors which are caused by illegal register accesses through CBB. When the bit is set, interrupt is used for reporting errors and magic code '0xdead2003' is returned. This change is only required for Tegra194 SoC as the config is moved to CBB register space for future SoC's. Also, remove unmapping the apbmisc_base as it's required to get the base address for accessing the misc register. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-05-12 01:46:43 +05:30
soc/tegra: fuse: Add stub for tegra_sku_info Drivers that use tegra_sku_info and have COMPILE_TEST are failing to be build due to the missing stub for tegra_sku_info. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20201104164923.21238-4-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-04 19:48:39 +03:00
soc/tegra: fuse: Add stubs needed for compile-testing Add missing stubs that will allow Tegra memory driver to be compile-tested by kernel build bots. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-05-28 02:54:04 +03:00
soc/tegra: fuse: Add stubs needed for compile testing Add stubs needed for compile-testing of tegra-cpuidle driver. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-09-12 23:29:02 +03:00
soc/tegra: Set ERD bit to mask inband errors Add a function to set the ERD (Error Response Disable) bit in the MISCREG_CCROC_ERR_CONFIG register from the Control Backbone (CBB) error handler driver. ERD bit allows masking of SError due to inband errors which are caused by illegal register accesses through CBB. When the bit is set, interrupt is used for reporting errors and magic code '0xdead2003' is returned. This change is only required for Tegra194 SoC as the config is moved to CBB register space for future SoC's. Also, remove unmapping the apbmisc_base as it's required to get the base address for accessing the misc register. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-05-12 01:46:43 +05:30
soc/tegra: fuse: Add stub for tegra_sku_info Drivers that use tegra_sku_info and have COMPILE_TEST are failing to be build due to the missing stub for tegra_sku_info. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20201104164923.21238-4-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-04 19:48:39 +03:00
ARM: tegra: move fuse exports to soc/tegra/fuse.h All fuse related functionality will move to a driver in the following patches. To prepare for this, export all the required functionality in a global header file and move all users of fuse.h to soc/tegra/fuse.h. While we're at it, remove tegra_bct_strapping, as its only user was removed in Commit a7cbe92cef27 ("ARM: tegra: remove tegra EMC scaling driver"). Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-12 18:36:36 +03:00
soc/tegra: Register SoC device Move this code from arch/arm/mach-tegra and make it common among 32-bit and 64-bit Tegra SoCs. This is slightly complicated by the fact that on 32-bit Tegra, the SoC device is used as the parent for all devices that are instantiated from device tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17 16:42:17 +02:00
ARM: tegra: Use a function to get the chip ID Instead of using a simple variable access to get at the Tegra chip ID, use a function so that we can run additional code. This can be used to determine where the chip ID is being accessed without being available. That in turn will be handy for resolving boot sequence dependencies in order to convert more code to regular initcalls rather than a sequence fixed by Tegra SoC setup code. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-11 09:52:41 +02:00
ARM: tegra: add function to read chipid Add function to read chip id from APB MISC registers. This function will also get called from clock driver to flush write operations on apb bus. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-11 13:16:19 +05:30
ARM: tegra: Move includes to include/soc/tegra In order to not clutter the include/linux directory with SoC specific headers, move the Tegra-specific headers out into a separate directory. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17 13:17:24 +02:00