2005-04-16 15:20:36 -07:00
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2012-10-13 10:46:48 +01:00
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2009-02-08 11:00:25 +05:30
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2009-02-06 20:47:58 +05:30
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2005-04-16 15:20:36 -07:00
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2011-07-26 17:04:15 -04:00
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2012-05-19 10:25:23 -04:00
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2005-04-16 15:20:36 -07:00
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2006-09-30 23:27:11 -07:00
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2005-04-16 15:20:36 -07:00
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2007-10-29 05:11:28 +00:00
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2005-04-16 15:20:36 -07:00
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2008-02-08 04:21:24 -08:00
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2005-04-16 15:20:36 -07:00
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2008-02-08 04:21:24 -08:00
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2005-04-16 15:20:36 -07:00
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2010-10-26 14:21:10 -07:00
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2008-01-31 03:57:36 -08:00
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2006-11-08 00:26:51 -08:00
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2005-08-13 13:55:44 -07:00
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2006-10-04 13:37:45 +02:00
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2005-04-16 15:20:36 -07:00
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2006-10-04 13:37:45 +02:00
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2008-12-12 09:51:16 +01:00
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2005-04-16 15:20:36 -07:00
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2009-06-19 08:08:50 +02:00
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2006-12-04 03:38:31 -07:00
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2008-12-12 09:51:16 +01:00
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2006-03-26 01:37:52 -08:00
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2005-04-16 15:20:36 -07:00
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2015-02-12 15:01:22 -08:00
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2005-04-16 15:20:36 -07:00
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PCI: Add pci_bus_addr_t
David Ahern reported that d63e2e1f3df9 ("sparc/PCI: Clip bridge windows
to fit in upstream windows") fails to boot on sparc/T5-8:
pci 0000:06:00.0: reg 0x184: can't handle BAR above 4GB (bus address 0x110204000)
The problem is that sparc64 assumed that dma_addr_t only needed to hold DMA
addresses, i.e., bus addresses returned via the DMA API (dma_map_single(),
etc.), while the PCI core assumed dma_addr_t could hold *any* bus address,
including raw BAR values. On sparc64, all DMA addresses fit in 32 bits, so
dma_addr_t is a 32-bit type. However, BAR values can be 64 bits wide, so
they don't fit in a dma_addr_t. d63e2e1f3df9 added new checking that
tripped over this mismatch.
Add pci_bus_addr_t, which is wide enough to hold any PCI bus address,
including both raw BAR values and DMA addresses. This will be 64 bits
on 64-bit platforms and on platforms with a 64-bit dma_addr_t. Then
dma_addr_t only needs to be wide enough to hold addresses from the DMA API.
[bhelgaas: changelog, bugzilla, Kconfig to ensure pci_bus_addr_t is at
least as wide as dma_addr_t, documentation]
Fixes: d63e2e1f3df9 ("sparc/PCI: Clip bridge windows to fit in upstream windows")
Fixes: 23b13bc76f35 ("PCI: Fail safely if we can't handle BARs larger than 4GB")
Link: http://lkml.kernel.org/r/CAE9FiQU1gJY1LYrxs+ma5LCTEEe4xmtjRG0aXJ9K_Tsu+m9Wuw@mail.gmail.com
Link: http://lkml.kernel.org/r/1427857069-6789-1-git-send-email-yinghai@kernel.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=96231
Reported-by: David Ahern <david.ahern@oracle.com>
Tested-by: David Ahern <david.ahern@oracle.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: David S. Miller <davem@davemloft.net>
CC: stable@vger.kernel.org # v3.19+
2015-05-27 17:23:51 -07:00
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2011-03-22 16:33:50 -07:00
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PCI: Add pci_bus_addr_t
David Ahern reported that d63e2e1f3df9 ("sparc/PCI: Clip bridge windows
to fit in upstream windows") fails to boot on sparc/T5-8:
pci 0000:06:00.0: reg 0x184: can't handle BAR above 4GB (bus address 0x110204000)
The problem is that sparc64 assumed that dma_addr_t only needed to hold DMA
addresses, i.e., bus addresses returned via the DMA API (dma_map_single(),
etc.), while the PCI core assumed dma_addr_t could hold *any* bus address,
including raw BAR values. On sparc64, all DMA addresses fit in 32 bits, so
dma_addr_t is a 32-bit type. However, BAR values can be 64 bits wide, so
they don't fit in a dma_addr_t. d63e2e1f3df9 added new checking that
tripped over this mismatch.
Add pci_bus_addr_t, which is wide enough to hold any PCI bus address,
including both raw BAR values and DMA addresses. This will be 64 bits
on 64-bit platforms and on platforms with a 64-bit dma_addr_t. Then
dma_addr_t only needs to be wide enough to hold addresses from the DMA API.
[bhelgaas: changelog, bugzilla, Kconfig to ensure pci_bus_addr_t is at
least as wide as dma_addr_t, documentation]
Fixes: d63e2e1f3df9 ("sparc/PCI: Clip bridge windows to fit in upstream windows")
Fixes: 23b13bc76f35 ("PCI: Fail safely if we can't handle BARs larger than 4GB")
Link: http://lkml.kernel.org/r/CAE9FiQU1gJY1LYrxs+ma5LCTEEe4xmtjRG0aXJ9K_Tsu+m9Wuw@mail.gmail.com
Link: http://lkml.kernel.org/r/1427857069-6789-1-git-send-email-yinghai@kernel.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=96231
Reported-by: David Ahern <david.ahern@oracle.com>
Tested-by: David Ahern <david.ahern@oracle.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: David S. Miller <davem@davemloft.net>
CC: stable@vger.kernel.org # v3.19+
2015-05-27 17:23:51 -07:00
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2011-03-22 16:33:50 -07:00
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2005-10-21 02:55:38 -04:00
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2008-09-02 15:28:45 -04:00
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2012-12-11 16:02:56 -08:00
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2006-06-12 15:49:31 -07:00
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2008-09-11 01:31:45 -07:00
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2008-09-11 01:31:50 -07:00
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2012-04-03 07:11:04 -06:00
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2009-01-06 14:40:39 -08:00
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|
atomic_t: Remove volatile from atomic_t definition
When looking at a performance problem on PowerPC, I noticed some awful code
generation:
c00000000051fc98: 3b 60 00 01 li r27,1
...
c00000000051fca0: 3b 80 00 00 li r28,0
...
c00000000051fcdc: 93 61 00 70 stw r27,112(r1)
c00000000051fce0: 93 81 00 74 stw r28,116(r1)
c00000000051fce4: 81 21 00 70 lwz r9,112(r1)
c00000000051fce8: 80 01 00 74 lwz r0,116(r1)
c00000000051fcec: 7d 29 07 b4 extsw r9,r9
c00000000051fcf0: 7c 00 07 b4 extsw r0,r0
c00000000051fcf4: 7c 20 04 ac lwsync
c00000000051fcf8: 7d 60 f8 28 lwarx r11,0,r31
c00000000051fcfc: 7c 0b 48 00 cmpw r11,r9
c00000000051fd00: 40 c2 00 10 bne- c00000000051fd10
c00000000051fd04: 7c 00 f9 2d stwcx. r0,0,r31
c00000000051fd08: 40 c2 ff f0 bne+ c00000000051fcf8
c00000000051fd0c: 4c 00 01 2c isync
We create two constants, write them out to the stack, read them straight back
in and sign extend them. What a mess.
It turns out this bad code is a result of us defining atomic_t as a
volatile int.
We removed the volatile attribute from the powerpc atomic_t definition years
ago, but commit ea435467500612636f8f4fb639ff6e76b2496e4b (atomic_t: unify all
arch definitions) added it back in.
To dig up an old quote from Linus:
> The fact is, volatile on data structures is a bug. It's a wart in the C
> language. It shouldn't be used.
>
> Volatile accesses in *code* can be ok, and if we have "atomic_read()"
> expand to a "*(volatile int *)&(x)->value", then I'd be ok with that.
>
> But marking data structures volatile just makes the compiler screw up
> totally, and makes code for initialization sequences etc much worse.
And screw up it does :)
With the volatile removed, we see much more reasonable code generation:
c00000000051f5b8: 3b 60 00 01 li r27,1
...
c00000000051f5c0: 3b 80 00 00 li r28,0
...
c00000000051fc7c: 7c 20 04 ac lwsync
c00000000051fc80: 7c 00 f8 28 lwarx r0,0,r31
c00000000051fc84: 7c 00 d8 00 cmpw r0,r27
c00000000051fc88: 40 c2 00 10 bne- c00000000051fc98
c00000000051fc8c: 7f 80 f9 2d stwcx. r28,0,r31
c00000000051fc90: 40 c2 ff f0 bne+ c00000000051fc80
c00000000051fc94: 4c 00 01 2c isync
Six instructions less.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-05-17 14:34:57 +10:00
|
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2009-01-06 14:40:39 -08:00
|
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|
atomic_t: Remove volatile from atomic_t definition
When looking at a performance problem on PowerPC, I noticed some awful code
generation:
c00000000051fc98: 3b 60 00 01 li r27,1
...
c00000000051fca0: 3b 80 00 00 li r28,0
...
c00000000051fcdc: 93 61 00 70 stw r27,112(r1)
c00000000051fce0: 93 81 00 74 stw r28,116(r1)
c00000000051fce4: 81 21 00 70 lwz r9,112(r1)
c00000000051fce8: 80 01 00 74 lwz r0,116(r1)
c00000000051fcec: 7d 29 07 b4 extsw r9,r9
c00000000051fcf0: 7c 00 07 b4 extsw r0,r0
c00000000051fcf4: 7c 20 04 ac lwsync
c00000000051fcf8: 7d 60 f8 28 lwarx r11,0,r31
c00000000051fcfc: 7c 0b 48 00 cmpw r11,r9
c00000000051fd00: 40 c2 00 10 bne- c00000000051fd10
c00000000051fd04: 7c 00 f9 2d stwcx. r0,0,r31
c00000000051fd08: 40 c2 ff f0 bne+ c00000000051fcf8
c00000000051fd0c: 4c 00 01 2c isync
We create two constants, write them out to the stack, read them straight back
in and sign extend them. What a mess.
It turns out this bad code is a result of us defining atomic_t as a
volatile int.
We removed the volatile attribute from the powerpc atomic_t definition years
ago, but commit ea435467500612636f8f4fb639ff6e76b2496e4b (atomic_t: unify all
arch definitions) added it back in.
To dig up an old quote from Linus:
> The fact is, volatile on data structures is a bug. It's a wart in the C
> language. It shouldn't be used.
>
> Volatile accesses in *code* can be ok, and if we have "atomic_read()"
> expand to a "*(volatile int *)&(x)->value", then I'd be ok with that.
>
> But marking data structures volatile just makes the compiler screw up
> totally, and makes code for initialization sequences etc much worse.
And screw up it does :)
With the volatile removed, we see much more reasonable code generation:
c00000000051f5b8: 3b 60 00 01 li r27,1
...
c00000000051f5c0: 3b 80 00 00 li r28,0
...
c00000000051fc7c: 7c 20 04 ac lwsync
c00000000051fc80: 7c 00 f8 28 lwarx r0,0,r31
c00000000051fc84: 7c 00 d8 00 cmpw r0,r27
c00000000051fc88: 40 c2 00 10 bne- c00000000051fc98
c00000000051fc8c: 7f 80 f9 2d stwcx. r28,0,r31
c00000000051fc90: 40 c2 ff f0 bne+ c00000000051fc80
c00000000051fc94: 4c 00 01 2c isync
Six instructions less.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-05-17 14:34:57 +10:00
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2009-01-06 14:40:39 -08:00
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2010-07-02 13:41:14 -04:00
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2005-04-16 15:20:36 -07:00
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2011-05-31 21:03:55 -07:00
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2012-06-27 11:07:19 +04:00
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2011-05-31 21:03:55 -07:00
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2012-06-27 11:07:19 +04:00
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2011-05-31 21:03:55 -07:00
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2012-06-27 11:07:19 +04:00
|
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|
2011-05-31 21:03:55 -07:00
|
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|
2015-06-10 12:53:06 -07:00
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2014-12-21 19:46:56 +01:00
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2009-02-06 20:47:58 +05:30
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2005-04-16 15:20:36 -07:00
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