kernel/linux
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ synced 2026-10-28 20:03:05 +00:00
Code Issues Releases Packages Activity
linux/drivers/memory/Kconfig

231 lines
8.1 KiB
Raw Normal View History

treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-19 13:07:45 +01:00
memory: emif: add basic infrastructure for EMIF driver EMIF is an SDRAM controller used in various Texas Instruments SoCs. EMIF supports, based on its revision, one or more of LPDDR2/DDR2/DDR3 protocols. Add the basic infrastructure for EMIF driver that includes driver registration, probe, parsing of platform data etc. Signed-off-by: Aneesh V <aneesh@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Benoit Cousson <b-cousson@ti.com> [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc] Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-04-27 17:54:05 +05:30
memory: Describe the MEMORY Kconfig entry Write short description about the entire memory controllers section. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-07-24 09:40:37 +02:00
memory: emif: add basic infrastructure for EMIF driver EMIF is an SDRAM controller used in various Texas Instruments SoCs. EMIF supports, based on its revision, one or more of LPDDR2/DDR2/DDR3 protocols. Add the basic infrastructure for EMIF driver that includes driver registration, probe, parsing of platform data etc. Signed-off-by: Aneesh V <aneesh@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Benoit Cousson <b-cousson@ti.com> [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc] Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-04-27 17:54:05 +05:30
memory: move jedec_ddr_data.c from lib/ to drivers/memory/ jedec_ddr_data.c exports 3 symbols, and all of them are only referenced from drivers/memory/{emif.c,of_memory.c} drivers/memory/ is a better location than lib/. I removed the Kconfig prompt "JEDEC DDR data" because it is only select'ed by TI_EMIF, and there is no other user. There is no good reason in making it a user-configurable CONFIG option. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-03 17:12:32 +09:00
memory: add ARM PL172 MultiPort Memory Controller driver This driver makes it possible to configure the static memory chip selects on the ARM PL172 MultiPort Memory Controller from a set of properties in DT. Configuration of dynamic memory is not supported and is left to the boot loader. The intended usage is to setup timing and configuration for static memory devices like NAND and NOR Flash before they are probed by a driver. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2015-07-13 23:20:11 +02:00
memory: add Atmel EBI (External Bus Interface) driver The EBI (External Bus Interface) is used to access external peripherals (NOR, SRAM, NAND, and other specific devices like ethernet controllers). Each device is assigned a CS line and an address range and can have its own configuration (timings, access mode, bus width, ...). This driver provides a generic DT binding to configure a device according to its requirements. For specific device controllers (like the NAND one) the SMC timings should be configured by the controller driver through the matrix and smc syscon regmaps. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-05-23 09:44:54 +02:00
memory: Enable compile testing for most of the drivers Most of the memory controller drivers do not depend on architecture specific code so can be compile tested to increase build coverage. When compile tested, do not enable them by default. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200724074038.5597-7-krzk@kernel.org
2020-07-24 09:40:15 +02:00
memory: add Atmel EBI (External Bus Interface) driver The EBI (External Bus Interface) is used to access external peripherals (NOR, SRAM, NAND, and other specific devices like ethernet controllers). Each device is assigned a CS line and an address range and can have its own configuration (timings, access mode, bus width, ...). This driver provides a generic DT binding to configure a device according to its requirements. For specific device controllers (like the NAND one) the SMC timings should be configured by the controller driver through the matrix and smc syscon regmaps. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-05-23 09:44:54 +02:00
memory: atmel-ebi: Simplify SMC config code New helpers/macros have been to atmel-smc.h introduced to simplify SMC regs manipulation. Rework the code to use those helpers, and simplify the ->xlate_config(), ->get_config() and ->apply_config() implementations. SMC configs are now stored in a struct atmel_smc_cs_conf object that directly contains registers values, which should help implementing ->suspend()/->resume() hooks. We can also get rid of those regmap fields (and the associated ->init() hook) which are not longer needed thanks to the atmel_[h]smc_cs_conf_{apply,get}() helpers. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-03-16 09:30:29 +01:00
memory: add Atmel EBI (External Bus Interface) driver The EBI (External Bus Interface) is used to access external peripherals (NOR, SRAM, NAND, and other specific devices like ethernet controllers). Each device is assigned a CS line and an address range and can have its own configuration (timings, access mode, bus width, ...). This driver provides a generic DT binding to configure a device according to its requirements. For specific device controllers (like the NAND one) the SMC timings should be configured by the controller driver through the matrix and smc syscon regmaps. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-05-23 09:44:54 +02:00
memory: brcmstb_dpfe: add separate entry for compile test Add separate entry for Broadcom STB DPFE driver, enabled by default on ARCH_BRCMSTB. This allows compile testing. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2020-07-24 19:40:16 +02:00
memory: brcmstb_dpfe: Allow building Broadcom STB DPFE as module Allow building the Broadcom STB DPFE driver as a module, it is already a platform driver proper with all of the resource releasing device managed. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Markus Mayer <mmayer@broadcom.com> Link: https://lore.kernel.org/r/20210924031459.8911-1-f.fainelli@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-09-23 20:14:59 -07:00
memory: brcmstb_dpfe: add separate entry for compile test Add separate entry for Broadcom STB DPFE driver, enabled by default on ARCH_BRCMSTB. This allows compile testing. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2020-07-24 19:40:16 +02:00
memory: brcmstb_memc: Add Broadcom STB memory controller driver Add support for configuring the Self Refresh Power Down (SRPD) inactivity timeout on Broadcom STB chips. This is used to conserve power when the DRAM activity is reduced. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220812222533.2428033-4-f.fainelli@gmail.com
2022-08-12 15:25:33 -07:00
memory: Add Baikal-T1 L2-cache Control Block driver Baikal-T1 SoC provides a way to tune the MIPS P5600 CM2 L2-cache performance up. It can be done by changing the L2-RAM Data/Tag/WS latencies in a dedicated register exposed by the system controller. The driver added by this commit provides a dts properties-based and sysfs-based interface for it. The device DT node is supposed to be a child of Baikal-T1 System Controller node. Link: https://lore.kernel.org/r/20200526125928.17096-7-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Paul Burton <paulburton@kernel.org> Cc: Olof Johansson <olof@lixom.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: soc@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-26 15:59:28 +03:00
memory: ti-aemif: introduce AEMIF driver Add new AEMIF driver for EMIF16 Texas Instruments controller. The EMIF16 module is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed at any given time via 4 chip selects with 64M byte access per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR are not supported. This controller is used on SoCs like Davinci, Keysone2 Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-02-24 19:26:11 +02:00
memory: Enable compile testing for most of the drivers Most of the memory controller drivers do not depend on architecture specific code so can be compile tested to increase build coverage. When compile tested, do not enable them by default. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200724074038.5597-7-krzk@kernel.org
2020-07-24 09:40:15 +02:00
memory: ti-aemif: introduce AEMIF driver Add new AEMIF driver for EMIF16 Texas Instruments controller. The EMIF16 module is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed at any given time via 4 chip selects with 64M byte access per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR are not supported. This controller is used on SoCs like Davinci, Keysone2 Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-02-24 19:26:11 +02:00
memory: emif: add basic infrastructure for EMIF driver EMIF is an SDRAM controller used in various Texas Instruments SoCs. EMIF supports, based on its revision, one or more of LPDDR2/DDR2/DDR3 protocols. Add the basic infrastructure for EMIF driver that includes driver registration, probe, parsing of platform data etc. Signed-off-by: Aneesh V <aneesh@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Benoit Cousson <b-cousson@ti.com> [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc] Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-04-27 17:54:05 +05:30
memory: Enable compile testing for most of the drivers Most of the memory controller drivers do not depend on architecture specific code so can be compile tested to increase build coverage. When compile tested, do not enable them by default. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200724074038.5597-7-krzk@kernel.org
2020-07-24 09:40:15 +02:00
memory: emif: add basic infrastructure for EMIF driver EMIF is an SDRAM controller used in various Texas Instruments SoCs. EMIF supports, based on its revision, one or more of LPDDR2/DDR2/DDR3 protocols. Add the basic infrastructure for EMIF driver that includes driver registration, probe, parsing of platform data etc. Signed-off-by: Aneesh V <aneesh@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Benoit Cousson <b-cousson@ti.com> [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc] Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-04-27 17:54:05 +05:30
memory: gpmc: Move omap gpmc code to live under drivers Just move to drivers as further clean-up can now happen there finally. Let's also add Roger and me to the MAINTAINERS so we get notified for any patches related to GPMC. Cc: Arnd Bergmann <arnd@arndb.de> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-11-20 09:13:42 -08:00
memory: omap-gpmc: Allow building as a module Allow OMAP_GPMC to be built as a module. When building this driver as a module, the symbol 'of_default_bus_match_table' will not be found as it is not being exported. The of_match_node() call is redundant anyways as of_platform_default_populate() already takes care of matching with 'of_default_bus_match_table'. So get rid of that call. This will also resolve the module build failure. Move compatible match table to the end where it is usually expected. Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20220426082611.24427-3-rogerq@kernel.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-04-26 11:26:11 +03:00
memory: omap-gpmc: Fix compile test on SPARC SPARC comes without CONFIG_OF_ADDRESS thus compile testing fails on linking: /usr/bin/sparc64-linux-gnu-ld: drivers/memory/omap-gpmc.o: in function `gpmc_probe_generic_child': omap-gpmc.c:(.text.unlikely+0x14ec): undefined reference to `of_platform_device_create' Fixes: ea0c0ad6b6eb ("memory: Enable compile testing for most of the drivers") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Roger Quadros <rogerq@ti.com> Link: https://lore.kernel.org/r/20200911143251.399-1-krzk@kernel.org
2020-09-11 16:32:51 +02:00
memory: omap-gpmc: OMAP_GPMC should depend on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 The Texas Instruments OMAP General Purpose Memory Controller (GPMC) is only present on TI OMAP2/3/4/5, Keystone, AM33xx, AM43x, DRA7xx, TI81xx, and K3 SoCs. Hence add a dependency on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3, to prevent asking the user about this driver when configuring a kernel without OMAP2+, Keystone, or K3 SoC family support. Fixes: be34f45f0d4aa91c ("memory: omap-gpmc: Make OMAP_GPMC config visible and selectable") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/f6780f572f882ed6ab5934321942cf2b412bf8d1.1652174849.git.geert+renesas@glider.be Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-05-10 11:29:13 +02:00
memory: omap-gpmc: Support general purpose input for WAITPINs OMAPs can have 2 to 4 WAITPINs that can be used as general purpose input if not used for memory wait state insertion. The first user will be the OMAP NAND chip to get the NAND read/busy status using gpiolib. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com>
2016-03-07 12:18:43 +02:00
memory: gpmc: Move omap gpmc code to live under drivers Just move to drivers as further clean-up can now happen there finally. Let's also add Roger and me to the MAINTAINERS so we get notified for any patches related to GPMC. Cc: Arnd Bergmann <arnd@arndb.de> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-11-20 09:13:42 -08:00
memory: omap-gpmc: Add Kconfig option for debug We support decoding the bootloader values if DEBUG is defined. But we also need to change the struct omap_hwmod flags to have HWMOD_INIT_NO_RESET to avoid the GPMC being reset during the boot. Otherwise just the default timings will be displayed instead of the bootloader configured timings. This also allows us to clean up the various GPMC related hwmod flags. For debugging, we only need HWMOD_INIT_NO_RESET, and HWMOD_INIT_NO_IDLE is not needed. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2015-06-01 19:22:10 -06:00
memory: omap-gpmc: Fix unselectable debug option for GPMC Commit 63aa945b1013 ("memory: omap-gpmc: Add Kconfig option for debug") added a debug option for GPMC, but somehow managed to keep it unselectable. This probably happened because I had some uncommitted changes and the GPMC option is selected in the platform specific Kconfig. Let's also update the description a bit, it does not mention that enabling the debug option also disables the reset of GPMC controller during the init as pointed out by Uwe Kleine-König <u.kleine-koenig@pengutronix.de> and Roger Quadros <rogerq@ti.com>. Fixes: 63aa945b1013 ("memory: omap-gpmc: Add Kconfig option for debug") Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-10-12 16:19:54 -07:00
memory: omap-gpmc: Add Kconfig option for debug We support decoding the bootloader values if DEBUG is defined. But we also need to change the struct omap_hwmod flags to have HWMOD_INIT_NO_RESET to avoid the GPMC being reset during the boot. Otherwise just the default timings will be displayed instead of the bootloader configured timings. This also allows us to clean up the various GPMC related hwmod flags. For debugging, we only need HWMOD_INIT_NO_RESET, and HWMOD_INIT_NO_IDLE is not needed. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2015-06-01 19:22:10 -06:00
memory: omap-gpmc: Fix unselectable debug option for GPMC Commit 63aa945b1013 ("memory: omap-gpmc: Add Kconfig option for debug") added a debug option for GPMC, but somehow managed to keep it unselectable. This probably happened because I had some uncommitted changes and the GPMC option is selected in the platform specific Kconfig. Let's also update the description a bit, it does not mention that enabling the debug option also disables the reset of GPMC controller during the init as pointed out by Uwe Kleine-König <u.kleine-koenig@pengutronix.de> and Roger Quadros <rogerq@ti.com>. Fixes: 63aa945b1013 ("memory: omap-gpmc: Add Kconfig option for debug") Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-10-12 16:19:54 -07:00
memory: omap-gpmc: Add Kconfig option for debug We support decoding the bootloader values if DEBUG is defined. But we also need to change the struct omap_hwmod flags to have HWMOD_INIT_NO_RESET to avoid the GPMC being reset during the boot. Otherwise just the default timings will be displayed instead of the bootloader configured timings. This also allows us to clean up the various GPMC related hwmod flags. For debugging, we only need HWMOD_INIT_NO_RESET, and HWMOD_INIT_NO_IDLE is not needed. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2015-06-01 19:22:10 -06:00
memory: ti-emif-sram: introduce relocatable suspend/resume handlers Certain SoCs like Texas Instruments AM335x and AM437x require parts of the EMIF PM code to run late in the suspend sequence from SRAM, such as saving and restoring the EMIF context and placing the memory into self-refresh. One requirement for these SoCs to suspend and enter its lowest power mode, called DeepSleep0, is that the PER power domain must be shut off. Because the EMIF (DDR Controller) resides within this power domain, it will lose context during a suspend operation, so we must save it so we can restore once we resume. However, we cannot execute this code from external memory, as it is not available at this point, so the code must be executed late in the suspend path from SRAM. This patch introduces a ti-emif-sram driver that includes several functions written in ARM ASM that are relocatable so the PM SRAM code can use them. It also allocates a region of writable SRAM to be used by the code running in the executable region of SRAM to save and restore the EMIF context. It can export a table containing the absolute addresses of the available PM functions so that other SRAM code can branch to them. This code is required for suspend/resume on AM335x and AM437x to work. In addition to this, to be able to share data structures between C and the ti-emif-sram-pm assembly code, we can automatically generate all of the C struct member offsets and sizes as macros by processing emif-asm-offsets.c into assembly code and then extracting the relevant data as is done for the generated platform asm-offsets.h files. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2015-06-17 14:52:10 -05:00
memory: ti-emif-sram: only build for ARMv7 The driver can be compile-tested on all ARM machines, but causes a failure when built for ARMv7-M: arm-linux-gnueabi-ld: error: drivers/memory/ti-emif-sram-pm.o: conflicting architecture profiles A/M Limit the target machines to configurations that have ARMv7 enabled. Fixes: ea0c0ad6b6eb ("memory: Enable compile testing for most of the drivers") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20201203230832.1481767-1-arnd@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-12-04 00:08:14 +01:00
memory: Enable compile testing for most of the drivers Most of the memory controller drivers do not depend on architecture specific code so can be compile tested to increase build coverage. When compile tested, do not enable them by default. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200724074038.5597-7-krzk@kernel.org
2020-07-24 09:40:15 +02:00
memory: ti-emif-sram: introduce relocatable suspend/resume handlers Certain SoCs like Texas Instruments AM335x and AM437x require parts of the EMIF PM code to run late in the suspend sequence from SRAM, such as saving and restoring the EMIF context and placing the memory into self-refresh. One requirement for these SoCs to suspend and enter its lowest power mode, called DeepSleep0, is that the PER power domain must be shut off. Because the EMIF (DDR Controller) resides within this power domain, it will lose context during a suspend operation, so we must save it so we can restore once we resume. However, we cannot execute this code from external memory, as it is not available at this point, so the code must be executed late in the suspend path from SRAM. This patch introduces a ti-emif-sram driver that includes several functions written in ARM ASM that are relocatable so the PM SRAM code can use them. It also allocates a region of writable SRAM to be used by the code running in the executable region of SRAM to save and restore the EMIF context. It can export a table containing the absolute addresses of the available PM functions so that other SRAM code can branch to them. This code is required for suspend/resume on AM335x and AM437x to work. In addition to this, to be able to share data structures between C and the ti-emif-sram-pm assembly code, we can automatically generate all of the C struct member offsets and sizes as macros by processing emif-asm-offsets.c into assembly code and then extracting the relevant data as is done for the generated platform asm-offsets.h files. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2015-06-17 14:52:10 -05:00
memory: dfl-emif: add the DFL EMIF private feature driver This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control. The purpose of memory clearing block is to zero out all private memory when FPGA is to be reprogrammed. This gives users a reliable method to prevent potential data leakage. [mdf@kernel.org: Fixed up ABI doc] Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20210107043714.991646-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-06 20:37:14 -08:00
drivers: memory: Introduce Marvell EBU Device Bus driver Marvell EBU SoCs such as Armada 370/XP, Orion5x (88f5xxx) and Discovery (mv78xx0) supports a Device Bus controller to access several kinds of memories and I/O devices (NOR, NAND, SRAM, FPGA). This commit adds a driver to handle this controller. So far only Armada 370, Armada XP and Discovery SoCs are supported. The driver must be registered through a device tree node; as explained in the binding document. For each child node in the device tree, this driver will: * set timing parameters * register a child device * setup an address decoding window, using the mbus driver Keep in mind the address decoding window setup is only a temporary hack. This code will be removed from this devbus driver as soon as a proper device tree binding for the mbus driver is added. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-04-23 16:21:26 -03:00
memory: Enable compile testing for most of the drivers Most of the memory controller drivers do not depend on architecture specific code so can be compile tested to increase build coverage. When compile tested, do not enable them by default. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200724074038.5597-7-krzk@kernel.org
2020-07-24 09:40:15 +02:00
drivers: memory: Introduce Marvell EBU Device Bus driver Marvell EBU SoCs such as Armada 370/XP, Orion5x (88f5xxx) and Discovery (mv78xx0) supports a Device Bus controller to access several kinds of memories and I/O devices (NOR, NAND, SRAM, FPGA). This commit adds a driver to handle this controller. So far only Armada 370, Armada XP and Discovery SoCs are supported. The driver must be registered through a device tree node; as explained in the binding document. For each child node in the device tree, this driver will: * set timing parameters * register a child device * setup an address decoding window, using the mbus driver Keep in mind the address decoding window setup is only a temporary hack. This code will be removed from this devbus driver as soon as a proper device tree binding for the mbus driver is added. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-04-23 16:21:26 -03:00
memory: Freescale CoreNet Coherency Fabric error reporting driver The CoreNet Coherency Fabric is part of the memory subsystem on some Freescale QorIQ chips. It can report coherency violations (e.g. due to misusing memory that is mapped noncoherent) as well as transactions that do not hit any local access window, or which hit a local access window with an invalid target ID. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@freescale.com>
2014-07-02 18:52:11 -05:00
memory: Enable compile testing for most of the drivers Most of the memory controller drivers do not depend on architecture specific code so can be compile tested to increase build coverage. When compile tested, do not enable them by default. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200724074038.5597-7-krzk@kernel.org
2020-07-24 09:40:15 +02:00
memory: Freescale CoreNet Coherency Fabric error reporting driver The CoreNet Coherency Fabric is part of the memory subsystem on some Freescale QorIQ chips. It can report coherency violations (e.g. due to misusing memory that is mapped noncoherent) as well as transactions that do not hit any local access window, or which hit a local access window with an invalid target ID. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@freescale.com>
2014-07-02 18:52:11 -05:00
powerpc: select MEMORY for FSL_IFC to not break existing .config files commit d2ae2e20fbdde5a65f3a5a153044ab1e5c53f7cc ("driver/memory:Move Freescale IFC driver to a common driver") introduces this build regression into the mpc85xx_defconfig: drivers/built-in.o: In function `fsl_ifc_nand_remove': drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev' drivers/built-in.o: In function `fsl_ifc_nand_probe': drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev' drivers/built-in.o: In function `match_bank': drivers/mtd/nand/fsl_ifc_nand.c:1013: undefined reference to `convert_ifc_address' drivers/built-in.o: In function `fsl_ifc_nand_probe': drivers/mtd/nand/fsl_ifc_nand.c:1059: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1080: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev' make: *** [vmlinux] Error 1 This happens because there is nothing to descend us into the drivers/memory directory in the mpc85xx_defconfig. It wasn't selecting CONFIG_MEMORY. So we never built drivers/memory/fsl_ifc.o and so we have nothing to link the above symbols against. Since the goal of the original commit was to relocate the driver to an arch independent location, it only makes sense to relocate the Kconfig setting there as well. But that alone won't fix the build failure; for that we ensure whoever selects FSL_IFC also selects MEMORY. Cc: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-02-19 17:46:40 -05:00
memory: Enable compile testing for most of the drivers Most of the memory controller drivers do not depend on architecture specific code so can be compile tested to increase build coverage. When compile tested, do not enable them by default. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200724074038.5597-7-krzk@kernel.org
2020-07-24 09:40:15 +02:00
memory: fsl_ifc: Allow selection of this driver when COMPILE_TEST=y It just makes maintainers' life easier by allowing them to compile-test this driver without having FSL_SOC, ARCH_LAYERSCAPE or SOC_LS1021A enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-07-09 22:09:37 +02:00
powerpc: select MEMORY for FSL_IFC to not break existing .config files commit d2ae2e20fbdde5a65f3a5a153044ab1e5c53f7cc ("driver/memory:Move Freescale IFC driver to a common driver") introduces this build regression into the mpc85xx_defconfig: drivers/built-in.o: In function `fsl_ifc_nand_remove': drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev' drivers/built-in.o: In function `fsl_ifc_nand_probe': drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev' drivers/built-in.o: In function `match_bank': drivers/mtd/nand/fsl_ifc_nand.c:1013: undefined reference to `convert_ifc_address' drivers/built-in.o: In function `fsl_ifc_nand_probe': drivers/mtd/nand/fsl_ifc_nand.c:1059: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1080: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev' make: *** [vmlinux] Error 1 This happens because there is nothing to descend us into the drivers/memory directory in the mpc85xx_defconfig. It wasn't selecting CONFIG_MEMORY. So we never built drivers/memory/fsl_ifc.o and so we have nothing to link the above symbols against. Since the goal of the original commit was to relocate the driver to an arch independent location, it only makes sense to relocate the Kconfig setting there as well. But that alone won't fix the build failure; for that we ensure whoever selects FSL_IFC also selects MEMORY. Cc: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-02-19 17:46:40 -05:00
memory: jz4780-nemc: driver for the NEMC on JZ4780 SoCs Add a driver for the NAND/External Memory Controller (NEMC) on JZ4780 and later SoCs. The primary function of this driver is to configure parameters, such as timings, for external memory devices using data supplied in the device tree. Devices connected to the NEMC are represented in the DT as children of the NEMC node, the driver uses optional properties specified in these child nodes to configure the parameters of each bank. Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-03-09 14:29:04 +00:00
memory: Kconfig: Drop dependency on MACH_JZ4780 for jz4780 Depending on MACH_JZ4780 prevent us from creating a generic kernel that works on more than one MIPS board. Instead, we just depend on MIPS being set. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-04 16:30:16 +02:00
drivers/memory/Kconfig: Add CONFIG_OF dependency JZ4780_NEMC doesn't depend on OF, and if OF isn't enabled we get this error: drivers/memory/jz4780-nemc.c: In function ‘jz4780_nemc_num_banks’: drivers/memory/jz4780-nemc.c:72:10: error: implicit declaration of function ‘of_read_number’; did you mean ‘down_read_nested’? [-Werror=implicit-function-declaration] bank = of_read_number(prop, 1); ^~~~~~~~~~~~~~ down_read_nested Make JZ4780_NEMC depend on OF. Fixes: ab99e11062c1 ("memory: jz4780-nemc: Allow selection of this driver when COMPILE_TEST=y") Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Anders Roxell <anders.roxell@linaro.org> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2018-07-25 11:19:28 +02:00
memory: jz4780-nemc: driver for the NEMC on JZ4780 SoCs Add a driver for the NAND/External Memory Controller (NEMC) on JZ4780 and later SoCs. The primary function of this driver is to configure parameters, such as timings, for external memory devices using data supplied in the device tree. Devices connected to the NEMC are represented in the DT as children of the NEMC node, the driver uses optional properties specified in these child nodes to configure the parameters of each bank. Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-03-09 14:29:04 +00:00
memory: mediatek: Add SMI driver This patch add SMI(Smart Multimedia Interface) driver. This driver is responsible to enable/disable iommu and control the power domain and clocks of each local arbiter. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2016-02-23 01:20:49 +08:00
memory: mtk-smi: Allow building as module Add support for building the SMI driver as module. Switch MTK_SMI to tristate, and add module_exit/module_license. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Link: https://lore.kernel.org/r/20210126060055.11050-1-yong.wu@mediatek.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2021-01-26 14:00:55 +08:00
memory: mediatek: Add SMI driver This patch add SMI(Smart Multimedia Interface) driver. This driver is responsible to enable/disable iommu and control the power domain and clocks of each local arbiter. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2016-02-23 01:20:49 +08:00
memory: davinci: add support for da8xx DDR2/mDDR controller Create a new driver for the da8xx DDR2/mDDR controller and implement support for writing to the Peripheral Bus Burst Priority Register. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> [nsekhar@ti.com: subject line adjustment] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2016-10-31 15:45:34 +01:00
memory: Enable compile testing for most of the drivers Most of the memory controller drivers do not depend on architecture specific code so can be compile tested to increase build coverage. When compile tested, do not enable them by default. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200724074038.5597-7-krzk@kernel.org
2020-07-24 09:40:15 +02:00
memory: davinci: add support for da8xx DDR2/mDDR controller Create a new driver for the da8xx DDR2/mDDR controller and implement support for writing to the Peripheral Bus Burst Priority Register. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> [nsekhar@ti.com: subject line adjustment] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2016-10-31 15:45:34 +01:00
memory: pl353: Add driver for arm pl353 static memory controller Add driver for arm pl353 static memory controller. This controller is used in Xilinx Zynq SoC for interfacing the NAND and NOR/SRAM memory devices. Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-12-06 18:17:34 +05:30
memory: Enable compile testing for most of the drivers Most of the memory controller drivers do not depend on architecture specific code so can be compile tested to increase build coverage. When compile tested, do not enable them by default. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200724074038.5597-7-krzk@kernel.org
2020-07-24 09:40:15 +02:00
memory: pl353-smc: fix compile test on !ARM_AMBA The pl353-smc driver uses module_amba_driver so it has a build dependency on CONFIG_ARM_AMBA: /usr/bin/arm-linux-gnueabi-ld: drivers/memory/pl353-smc.o: in function `pl353_smc_driver_init': pl353-smc.c:(.init.text+0x10): undefined reference to `amba_driver_register' However it still can be compile tested on platforms other than ARM, which in practice is limited to those selecting ARM_AMBA (so only ARM64). Fixes: ea0c0ad6b6eb ("memory: Enable compile testing for most of the drivers") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20201029193357.389593-1-krzk@kernel.org
2020-10-29 20:33:57 +01:00
memory: pl353: Add driver for arm pl353 static memory controller Add driver for arm pl353 static memory controller. This controller is used in Xilinx Zynq SoC for interfacing the NAND and NOR/SRAM memory devices. Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-12-06 18:17:34 +05:30
memory: add Renesas RPC-IF driver Add the memory driver for Renesas RPC-IF which registers either SPI or HyperFLash device depending on the contents of the device tree subnode. It also provides the absract "back end" device APIs that can be used by the "front end" SPI/MTD drivers to talk to the real hardware. Based on the original patch by Mason Yang <masonccyang@mxic.com.tw>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Link: https://lore.kernel.org/r/9a3606ec-d4d0-c63a-4fb6-631ab38e621c@cogentembedded.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-06-16 23:03:48 +03:00
memory: Enable compile testing for most of the drivers Most of the memory controller drivers do not depend on architecture specific code so can be compile tested to increase build coverage. When compile tested, do not enable them by default. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200724074038.5597-7-krzk@kernel.org
2020-07-24 09:40:15 +02:00
memory: add Renesas RPC-IF driver Add the memory driver for Renesas RPC-IF which registers either SPI or HyperFLash device depending on the contents of the device tree subnode. It also provides the absract "back end" device APIs that can be used by the "front end" SPI/MTD drivers to talk to the real hardware. Based on the original patch by Mason Yang <masonccyang@mxic.com.tw>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Link: https://lore.kernel.org/r/9a3606ec-d4d0-c63a-4fb6-631ab38e621c@cogentembedded.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-06-16 23:03:48 +03:00
memory: renesas-rpc-if: RENESAS_RPCIF should select RESET_CONTROLLER The Renesas RPC-IF driver calls devm_reset_control_get_exclusive(), which returns -ENOTSUPP if CONFIG_RESET_CONTROLLER is not enabled. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/e443aa66d146da5646b7ebece8876545b8621063.1633447756.git.geert+renesas@glider.be Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-10-05 17:29:22 +02:00
memory: add Renesas RPC-IF driver Add the memory driver for Renesas RPC-IF which registers either SPI or HyperFLash device depending on the contents of the device tree subnode. It also provides the absract "back end" device APIs that can be used by the "front end" SPI/MTD drivers to talk to the real hardware. Based on the original patch by Mason Yang <masonccyang@mxic.com.tw>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Link: https://lore.kernel.org/r/9a3606ec-d4d0-c63a-4fb6-631ab38e621c@cogentembedded.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-06-16 23:03:48 +03:00
memory: renesas-rpc-if: Add RZ/G2 to Kconfig description The Renesas RPC-IF is present on the RZ/G2 Series. Add that to the description. Suggested-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210102115412.3402059-2-aford173@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2021-01-02 05:54:10 -06:00
memory: add Renesas RPC-IF driver Add the memory driver for Renesas RPC-IF which registers either SPI or HyperFLash device depending on the contents of the device tree subnode. It also provides the absract "back end" device APIs that can be used by the "front end" SPI/MTD drivers to talk to the real hardware. Based on the original patch by Mason Yang <masonccyang@mxic.com.tw>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Link: https://lore.kernel.org/r/9a3606ec-d4d0-c63a-4fb6-631ab38e621c@cogentembedded.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-06-16 23:03:48 +03:00
memory: stm32-fmc2-ebi: add STM32 FMC2 EBI controller driver The driver adds the support for the STMicroelectronics FMC2 EBI controller found on STM32MP SOCs. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1591975362-22009-5-git-send-email-christophe.kerello@st.com
2020-06-12 17:22:40 +02:00
memory: stm32-fmc2-ebi: depends on ARCH_STM32 instead of MACH_STM32MP157 To be able to compile the driver on all STM32MP SOCs, we move the "depends on" on ARCH_STM32. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Link: https://lore.kernel.org/r/20230324155105.826063-2-christophe.kerello@foss.st.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-03-24 16:51:04 +01:00
memory: stm32-fmc2-ebi: add STM32 FMC2 EBI controller driver The driver adds the support for the STMicroelectronics FMC2 EBI controller found on STM32MP SOCs. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1591975362-22009-5-git-send-email-christophe.kerello@st.com
2020-06-12 17:22:40 +02:00
memory: Add support for Exynos SROM driver This patch adds Exynos SROM controller driver which will handle save restore of SROM registers during S2R. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> [p.fedin@samsung.com: tested on SMDK5410] Tested-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org> [k.kozlowski: Minor COMPILE_TEST adjustments in Kconfig entries] Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
2016-04-11 13:12:24 +05:30
memory: Add NVIDIA Tegra memory controller support The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements. This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead. The Tegra SMMU operates on memory clients and SWGROUPs. A memory client is a unidirectional, special-purpose DMA master. A SWGROUP represents a set of memory clients that form a logical functional unit corresponding to a single device. Typically a device has two clients: one client for read transactions and one client for write transactions, but there are also devices that have only read clients, but many of them (such as the display controllers). Because there is no 1:1 relationship between memory clients and devices the driver keeps a table of memory clients and the SWGROUPs that they belong to per SoC. Note that this is an exception and due to the fact that the SMMU is tightly integrated with the rest of the Tegra SoC. The use of these tables is discouraged in drivers for generic IOMMU devices such as the ARM SMMU because the same IOMMU could be used in any number of SoCs and keeping such tables for each SoC would not scale. Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-16 09:24:44 +02:00
memory: emif: add basic infrastructure for EMIF driver EMIF is an SDRAM controller used in various Texas Instruments SoCs. EMIF supports, based on its revision, one or more of LPDDR2/DDR2/DDR3 protocols. Add the basic infrastructure for EMIF driver that includes driver registration, probe, parsing of platform data etc. Signed-off-by: Aneesh V <aneesh@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Benoit Cousson <b-cousson@ti.com> [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc] Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-04-27 17:54:05 +05:30