kernel/linux
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ synced 2026-11-13 07:31:07 +00:00
Code Issues Releases Packages Activity
linux/drivers/mailbox/Kconfig

297 lines
10 KiB
Raw Normal View History

treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-19 13:07:45 +01:00
ARM / highbank: add support for pl320 IPC The pl320 IPC allows for interprocessor communication between the highbank A9 and the EnergyCore Management Engine. The pl320 implements a straightforward mailbox protocol. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-01-28 16:13:14 +00:00
mailbox: arm_mhu: add driver for ARM MHU controller Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Andy Green <andy.green@linaro.org> Signed-off-by: Vincent Yang <vincent.yang@socionext.com> Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
2014-06-26 19:09:42 +05:30
mailbox: apple: Add driver for Apple mailboxes Apple SoCs such as the M1 come with various co-processors. Mailboxes are used to communicate with those. This driver adds support for two variants of those mailboxes. Signed-off-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-10-25 08:22:04 +02:00
mailbox: arm_mhu: add driver for ARM MHU controller Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Andy Green <andy.green@linaro.org> Signed-off-by: Vincent Yang <vincent.yang@socionext.com> Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
2014-06-26 19:09:42 +05:30
mailbox: arm_mhuv2: Add driver This adds driver for the ARM MHUv2 (Message Handling Unit) mailbox controller. This is based on the accepted DT bindings of the controller and supports combination of both transport protocols, i.e. doorbell and data-transfer. Transmitting and receiving data through the mailbox framework is done through struct arm_mhuv2_mbox_msg. Based on the initial work done by Morten Borup Petersen from ARM. Co-developed-by: Tushar Khandelwal <tushar.khandelwal@arm.com> Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com> Tested-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-11-17 15:32:06 +05:30
mailbox: Add support for i.MX messaging unit The i.MX Messaging Unit is a two side block which allows applications implement communication over this sides. The MU includes the following features: - Messaging control by interrupts or by polling - Four general-purpose interrupt requests reflected to the other side - Three general-purpose flags reflected to the other side - Four receive registers with maskable interrupt - Four transmit registers with maskable interrupt Reviewed-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-08-03 07:29:19 +02:00
mailbox: Add Platform Message-Handling-Unit variant driver Add Message-Handling-Unit driver for platform variants as mailbox controller. Actually, only the Amlogic Meson GXBB SoC MHU is supported. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-08-18 12:10:25 +02:00
ARM / highbank: add support for pl320 IPC The pl320 IPC allows for interprocessor communication between the highbank A9 and the EnergyCore Management Engine. The pl320 implements a straightforward mailbox protocol. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-01-28 16:13:14 +00:00
mailbox: Add support for Armada 37xx rWTM mailbox This adds support for the mailbox via which the kernel can communicate with the firmware running on the secure processor of the Armada 37xx SOC. The rWTM secure processor has access to internal eFuses and cryptographic circuits, such as the Entropy Bit Generator to generate true random numbers. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-03-31 05:15:33 +02:00
mailbox/omap: move the OMAP mailbox framework to drivers The mailbox hardware (in OMAP) uses a queued mailbox interrupt mechanism that provides a communication channel between processors through a set of registers and their associated interrupt signals by sending and receiving messages. The OMAP mailbox framework/driver code is moved to be under drivers/mailbox, in preparation for adapting to a common mailbox driver framework. This allows the build for OMAP mailbox to be enabled (it was disabled during the multi-platform support). As part of the migration from plat and mach code: - Kconfig symbols have been renamed to build OMAP1 or OMAP2+ drivers. - mailbox.h under plat-omap/plat/include has been split into a public and private header files. The public header has only the API related functions and types. - The module name mailbox.ko from plat-omap is changed to omap-mailbox.ko - The module name mailbox_mach.ko from mach-omapX is changed as mailbox_omap1.ko for OMAP1 mailbox_omap2.ko for OMAP2+ Cc: Tony Lindgren <tony@atomide.com> [gregkh@linuxfoundation.org: ack for staging part] Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Omar Ramirez Luna <omar.ramirez@copitl.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2013-03-12 17:55:29 -05:00
mailbox: omap: Add support for TI K3 SoCs The TI K3 AM65x and J721E family of SoCs have a new Mailbox IP that is based on the existing Mailbox IP present in OMAP architecture based SoCs. Each instance of the legacy OMAP Mailbox IP is now a single cluster within the newer Mailbox IP instance on K3 architecture based SoCs. A single K3 Mailbox IP instance has multiple clusters with each cluster providing the same functionality as the existing OMAP Mailbox IP. Reuse the existing OMAP Mailbox driver to extend the support for this newer IP present within the Main NavSS block on K3 SoCs. The K3 family of SoCs use 64-bit ARMv8 processors for running Linux, so the driver is also enhanced to deal with the differences between the 32-bit message payloads and the 64-bit pointers used by the client drivers. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-06-04 12:01:46 -05:00
mailbox/omap: move the OMAP mailbox framework to drivers The mailbox hardware (in OMAP) uses a queued mailbox interrupt mechanism that provides a communication channel between processors through a set of registers and their associated interrupt signals by sending and receiving messages. The OMAP mailbox framework/driver code is moved to be under drivers/mailbox, in preparation for adapting to a common mailbox driver framework. This allows the build for OMAP mailbox to be enabled (it was disabled during the multi-platform support). As part of the migration from plat and mach code: - Kconfig symbols have been renamed to build OMAP1 or OMAP2+ drivers. - mailbox.h under plat-omap/plat/include has been split into a public and private header files. The public header has only the API related functions and types. - The module name mailbox.ko from plat-omap is changed to omap-mailbox.ko - The module name mailbox_mach.ko from mach-omapX is changed as mailbox_omap1.ko for OMAP1 mailbox_omap2.ko for OMAP2+ Cc: Tony Lindgren <tony@atomide.com> [gregkh@linuxfoundation.org: ack for staging part] Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Omar Ramirez Luna <omar.ramirez@copitl.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2013-03-12 17:55:29 -05:00
mailbox/omap: remove OMAP1 mailbox driver There are no existing users for OMAP1 mailbox driver in kernel. Commit ab6f775 "Removing dead OMAP_DSP" has cleaned up all the dead code related to the only possible user, including the creation of the mailbox platform device. Remove this stale driver so that the OMAP mailbox driver can be simplified and streamlined better for converting to mailbox framework. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-06-24 19:43:38 -05:00
mailbox/omap: move the OMAP mailbox framework to drivers The mailbox hardware (in OMAP) uses a queued mailbox interrupt mechanism that provides a communication channel between processors through a set of registers and their associated interrupt signals by sending and receiving messages. The OMAP mailbox framework/driver code is moved to be under drivers/mailbox, in preparation for adapting to a common mailbox driver framework. This allows the build for OMAP mailbox to be enabled (it was disabled during the multi-platform support). As part of the migration from plat and mach code: - Kconfig symbols have been renamed to build OMAP1 or OMAP2+ drivers. - mailbox.h under plat-omap/plat/include has been split into a public and private header files. The public header has only the API related functions and types. - The module name mailbox.ko from plat-omap is changed to omap-mailbox.ko - The module name mailbox_mach.ko from mach-omapX is changed as mailbox_omap1.ko for OMAP1 mailbox_omap2.ko for OMAP2+ Cc: Tony Lindgren <tony@atomide.com> [gregkh@linuxfoundation.org: ack for staging part] Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Omar Ramirez Luna <omar.ramirez@copitl.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2013-03-12 17:55:29 -05:00
Mailbox: Add support for Platform Communication Channel ACPI 5.0+ spec defines a generic mode of communication between the OS and a platform such as the BMC. This medium (PCC) is typically used by CPPC (ACPI CPU Performance management), RAS (ACPI reliability protocol) and MPST (ACPI Memory power states). This patch adds PCC support as a Mailbox Controller. As of ACPI v5.1 there is no provision for clients to lookup mailbox controllers in a way that Linux expects. e.g. in DT the clients can list the mailboxes they can associate with in the DT binding and then provide a unique index to lookup a channel within a mailbox. Since the ACPI spec doesn't have anything similar, we introduce a mailbox controller specific API so that when the client calls it, we know to lookup in the context of a specific controller. This also helps in keeping a consistent interface across DT and ACPI for such drivers. This patch implements basic PCC support using the ACPI v5.1 structures. IRQ mode support will be provided as follow up patches. Signed-off-by: Ashwin Chaugule <ashwin.chaugule@linaro.org> Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2014-11-12 19:59:38 -05:00
mailbox: rockchip: Add Rockchip mailbox driver This driver is found on RK3368 SoCs. The Mailbox module is a simple APB peripheral that allows both the Cortex-A53 MCU system to communicate by writing operation to generate interrupt. The registers are accessible by both CPU via APB interface. The Mailbox has the following main features: 1) Support dual-core system: Cortex-A53 and MCU. 2) Support APB interface. 3) Support four mailbox elements, each element includes one data word, one command word register and one flag bit that can represent one interrupt. 4) Four interrupts to Cortex-A53. 5) Four interrupts to MCU. 6) Provide 32 lock registers for software to use to indicate whether mailbox is occupied. [Jassi: Removed unused variable buf_base] Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2015-10-27 15:31:45 +08:00
mailbox: fix various typos in comments Fix trivial typos in mailbox driver comments. s/Intergrated/Integrated/ s/extenstion/extension/ s/atleast/at least/ s/commnunication/communication/ s/assgined/assigned/ s/commnunication/communication/ s/recevied/received/ s/succeded/succeeded/ s/implmentation/implementation/ s/definiation/definition/ s/traget/target/ s/wont/won't/ Cc: trivial@kernel.org Signed-off-by: Tom Saeger <tom.saeger@oracle.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-03-12 19:31:10 -07:00
mailbox: rockchip: Add Rockchip mailbox driver This driver is found on RK3368 SoCs. The Mailbox module is a simple APB peripheral that allows both the Cortex-A53 MCU system to communicate by writing operation to generate interrupt. The registers are accessible by both CPU via APB interface. The Mailbox has the following main features: 1) Support dual-core system: Cortex-A53 and MCU. 2) Support APB interface. 3) Support four mailbox elements, each element includes one data word, one command word register and one flag bit that can represent one interrupt. 4) Four interrupts to Cortex-A53. 5) Four interrupts to MCU. 6) Provide 32 lock registers for software to use to indicate whether mailbox is occupied. [Jassi: Removed unused variable buf_base] Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2015-10-27 15:31:45 +08:00
Mailbox: Add support for Platform Communication Channel ACPI 5.0+ spec defines a generic mode of communication between the OS and a platform such as the BMC. This medium (PCC) is typically used by CPPC (ACPI CPU Performance management), RAS (ACPI reliability protocol) and MPST (ACPI Memory power states). This patch adds PCC support as a Mailbox Controller. As of ACPI v5.1 there is no provision for clients to lookup mailbox controllers in a way that Linux expects. e.g. in DT the clients can list the mailboxes they can associate with in the DT binding and then provide a unique index to lookup a channel within a mailbox. Since the ACPI spec doesn't have anything similar, we introduce a mailbox controller specific API so that when the client calls it, we know to lookup in the context of a specific controller. This also helps in keeping a consistent interface across DT and ACPI for such drivers. This patch implements basic PCC support using the ACPI v5.1 structures. IRQ mode support will be provided as follow up patches. Signed-off-by: Ashwin Chaugule <ashwin.chaugule@linaro.org> Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2014-11-12 19:59:38 -05:00
PCC: Disable compilation by default PCC is made selectable only by clients which use it. e.g. CPPC Default it to disabled so that it is not included accidentally on platforms which dont use it. Signed-off-by: Ashwin Chaugule <ashwin.chaugule@linaro.org> Reviewed-by: Al Stone <al.stone@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2015-08-05 09:40:31 -04:00
Mailbox: Add support for Platform Communication Channel ACPI 5.0+ spec defines a generic mode of communication between the OS and a platform such as the BMC. This medium (PCC) is typically used by CPPC (ACPI CPU Performance management), RAS (ACPI reliability protocol) and MPST (ACPI Memory power states). This patch adds PCC support as a Mailbox Controller. As of ACPI v5.1 there is no provision for clients to lookup mailbox controllers in a way that Linux expects. e.g. in DT the clients can list the mailboxes they can associate with in the DT binding and then provide a unique index to lookup a channel within a mailbox. Since the ACPI spec doesn't have anything similar, we introduce a mailbox controller specific API so that when the client calls it, we know to lookup in the context of a specific controller. This also helps in keeping a consistent interface across DT and ACPI for such drivers. This patch implements basic PCC support using the ACPI v5.1 structures. IRQ mode support will be provided as follow up patches. Signed-off-by: Ashwin Chaugule <ashwin.chaugule@linaro.org> Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2014-11-12 19:59:38 -05:00
mailbox: Add Altera mailbox driver The Altera mailbox allows for interprocessor communication. It supports only one channel and work as either sender or receiver. Signed-off-by: Ley Foon Tan <lftan@altera.com>
2015-02-04 16:32:18 +08:00
mailbox: altera: Add dependency on HAS_IOMEM Not all architectures have io memory. Fixes: drivers/built-in.o: In function `altera_mbox_probe': mailbox-altera.c:(.text+0x409fd2): undefined reference to `devm_ioremap_resource' Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2015-05-04 20:59:46 +02:00
mailbox: Add Altera mailbox driver The Altera mailbox allows for interprocessor communication. It supports only one channel and work as either sender or receiver. Signed-off-by: Ley Foon Tan <lftan@altera.com>
2015-02-04 16:32:18 +08:00
mailbox: Enable BCM2835 mailbox support This mailbox driver provides a single mailbox channel to write 32-bit values to the VPU and get a 32-bit response. The Raspberry Pi firmware uses this mailbox channel to implement firmware calls, while Roku 2 (despite being derived from the same firmware tree) doesn't. The driver was originally submitted by Lubomir, based on the out-of-tree 2708 mailbox driver. Eric Anholt fixed it up for upstreaming, with the major functional change being that it now has no notion of multiple channels (since that is a firmware-dependent concept) and instead the raspberrypi-firmware driver will do that bit-twiddling in its own messages. [Jassi: made the 'mbox_chan_ops' struct as const and removed a redundant variable] Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Craig McGeachie <slapdau@yahoo.com.au> Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2015-05-05 13:27:45 -07:00
mailbox: Add support for ST's Mailbox IP ST's platforms currently support a maximum of 5 Mailboxes, one for each of the supported co-processors situated on the platform. Each Mailbox is divided up into 4 instances which consist of 32 channels. Messages are passed between the application and co-processors using shared memory areas. It is the Client's responsibility to manage these areas. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2015-10-16 08:21:28 +01:00
mailbox: Introduce TI message manager driver Support for TI Message Manager Module. This hardware block manages a bunch of hardware queues meant for communication between processor entities. Clients sitting on top of this would manage the required protocol for communicating with the counterpart entities. For more details on TI Message Manager hardware block, see documentation that will is available here: http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf Chapter 8.1(Message Manager) Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-03-16 19:23:14 -05:00
drivers: mailbox: Make ti-msgmr driver depend on ARCH_K3 ti-msgmr driver can support K3 platforms as well. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-08-27 19:53:11 -05:00
mailbox: Introduce TI message manager driver Support for TI Message Manager Module. This hardware block manages a bunch of hardware queues meant for communication between processor entities. Clients sitting on top of this would manage the required protocol for communicating with the counterpart entities. For more details on TI Message Manager hardware block, see documentation that will is available here: http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf Chapter 8.1(Message Manager) Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-03-16 19:23:14 -05:00
drivers: mailbox: Make ti-msgmr driver depend on ARCH_K3 ti-msgmr driver can support K3 platforms as well. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-08-27 19:53:11 -05:00
mailbox: Introduce TI message manager driver Support for TI Message Manager Module. This hardware block manages a bunch of hardware queues meant for communication between processor entities. Clients sitting on top of this would manage the required protocol for communicating with the counterpart entities. For more details on TI Message Manager hardware block, see documentation that will is available here: http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf Chapter 8.1(Message Manager) Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-03-16 19:23:14 -05:00
mailbox: Add support for Hi3660 mailbox Hi3660 mailbox controller is used to send message within multiple processors, MCU, HIFI, etc. It supports 32 mailbox channels and every channel can only be used for single transferring direction. Once the channel is enabled, it needs to specify the destination interrupt and acknowledge interrupt, these two interrupt vectors are used to create the connection between the mailbox and interrupt controllers. The data transferring supports two modes, one is named as "automatic acknowledge" mode so after send message the kernel doesn't need to wait for acknowledge from remote and directly return; there have another mode is to rely on handling interrupt for acknowledge. This commit is for initial version driver, which only supports "automatic acknowledge" mode to support CPU clock, which is the only one consumer to use mailbox and has been verified. Later may enhance this driver for interrupt mode (e.g. for supporting HIFI). Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Ruyi Wang <wangruyi@huawei.com> Signed-off-by: Kaihua Zhong <zhongkaihua@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-02-28 12:54:54 +08:00
mailbox/drivers/hisi: Consolidate the Kconfig for the MAILBOX The current defconfig is inconsistent as it selects the mailbox and the clock for the hi6220 and the hi3660 without having their Kconfigs making sure the dependencies are correct. It ends up when selecting different versions for the kernel (for example when git bisecting) those options disappear and they don't get back, leading to unexpected behaviors. In our case, the cpufreq driver does no longer work because the clock fails to initialize due to the clock stub and the mailbox missing. In order to have the dependencies correctly set when defaulting, let's do the same as commit 3a49afb84ca074e ("clk: enable hi655x common clk automatically") where we select automatically the driver when the parent driver is selected. With sensible defaults in place, we can leave other choices for EXPERT. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-05-22 22:54:49 +02:00
mailbox: Add support for Hi3660 mailbox Hi3660 mailbox controller is used to send message within multiple processors, MCU, HIFI, etc. It supports 32 mailbox channels and every channel can only be used for single transferring direction. Once the channel is enabled, it needs to specify the destination interrupt and acknowledge interrupt, these two interrupt vectors are used to create the connection between the mailbox and interrupt controllers. The data transferring supports two modes, one is named as "automatic acknowledge" mode so after send message the kernel doesn't need to wait for acknowledge from remote and directly return; there have another mode is to rely on handling interrupt for acknowledge. This commit is for initial version driver, which only supports "automatic acknowledge" mode to support CPU clock, which is the only one consumer to use mailbox and has been verified. Later may enhance this driver for interrupt mode (e.g. for supporting HIFI). Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Ruyi Wang <wangruyi@huawei.com> Signed-off-by: Kaihua Zhong <zhongkaihua@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-02-28 12:54:54 +08:00
mailbox: Hi6220: add mailbox driver Add driver for Hi6220 mailbox, the mailbox communicates with MCU; for sending data, it can support two methods for low level implementation: one is to use interrupt as acknowledge, another is automatic mode which without any acknowledge. These two methods have been supported in the driver. For receiving data, it will depend on the interrupt to notify the channel has incoming message. Now mailbox driver is used to send message to MCU to control dynamic voltage and frequency scaling for CPU, GPU and DDR. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-02-15 21:50:24 +08:00
mailbox/drivers/hisi: Consolidate the Kconfig for the MAILBOX The current defconfig is inconsistent as it selects the mailbox and the clock for the hi6220 and the hi3660 without having their Kconfigs making sure the dependencies are correct. It ends up when selecting different versions for the kernel (for example when git bisecting) those options disappear and they don't get back, leading to unexpected behaviors. In our case, the cpufreq driver does no longer work because the clock fails to initialize due to the clock stub and the mailbox missing. In order to have the dependencies correctly set when defaulting, let's do the same as commit 3a49afb84ca074e ("clk: enable hi655x common clk automatically") where we select automatically the driver when the parent driver is selected. With sensible defaults in place, we can leave other choices for EXPERT. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-05-22 22:54:49 +02:00
mailbox: Hi6220: add mailbox driver Add driver for Hi6220 mailbox, the mailbox communicates with MCU; for sending data, it can support two methods for low level implementation: one is to use interrupt as acknowledge, another is automatic mode which without any acknowledge. These two methods have been supported in the driver. For receiving data, it will depend on the interrupt to notify the channel has incoming message. Now mailbox driver is used to send message to MCU to control dynamic voltage and frequency scaling for CPU, GPU and DDR. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-02-15 21:50:24 +08:00
mailbox: Add generic mechanism for testing Mailbox Controllers This particular Client implementation uses shared memory in order to pass messages between Mailbox users; however, it can be easily hacked to support any type of Controller. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2015-10-16 08:21:30 +01:00
mailbox: Fix dependencies for !HAS_IOMEM archs Not every arch has io memory. So, unbreak the build by fixing the dependencies. Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-01-25 23:24:09 +01:00
mailbox: Add generic mechanism for testing Mailbox Controllers This particular Client implementation uses shared memory in order to pass messages between Mailbox users; however, it can be easily hacked to support any type of Controller. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2015-10-16 08:21:30 +01:00
mbox: add polarfire soc system controller mailbox This driver adds support for the single mailbox channel of the MSS system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-24 16:00:55 +01:00
mailbox: Introduce Qualcomm APCS IPC driver This implements a driver that exposes the IPC bits found in the APCS Global block in various Qualcomm platforms. The bits are used to signal inter-processor communication signals from the application CPU to other masters. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2017-05-27 16:14:04 -07:00
mailbox: Add Tegra HSP driver This driver exposes a mailbox interface for interprocessor communication using the Hardware Synchronization Primitives (HSP) module's doorbell mechanism. There are multiple HSP instances and they provide additional features such as shared mailboxes, shared and arbitrated semaphores. A driver for a remote processor can use the mailbox client provided by the HSP driver and build an IPC protocol on top of this synchronization mechanism. Based on work by Joseph Lo <josephl@nvidia.com>. Acked-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-19 19:19:39 +02:00
mailbox: tegra: relax TEGRA_HSP_MBOX Kconfig dependencies With the addition of the ARCH_TEGRA_194_SOC driver, we get a new Kconfig warning: warning: (ARCH_TEGRA_186_SOC && ARCH_TEGRA_194_SOC) selects TEGRA_HSP_MBOX which has unmet direct dependencies (MAILBOX && ARCH_TEGRA_186_SOC) It looks like the dependency is a bit too strict here, allowing the driver to be built for any Tegra chip avoids the problem. Fixes: 6f9ed07fde03 ("soc/tegra: Add Tegra194 SoC configuration option") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-03-13 13:11:43 +01:00
mailbox: Add Tegra HSP driver This driver exposes a mailbox interface for interprocessor communication using the Hardware Synchronization Primitives (HSP) module's doorbell mechanism. There are multiple HSP instances and they provide additional features such as shared mailboxes, shared and arbitrated semaphores. A driver for a remote processor can use the mailbox client provided by the HSP driver and build an IPC protocol on top of this synchronization mechanism. Based on work by Joseph Lo <josephl@nvidia.com>. Acked-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-19 19:19:39 +02:00
mailbox: Add support for APM X-Gene platform mailbox driver X-Gene mailbox controller provides 8 mailbox channels, with each channel has a dedicated interrupt line. Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Duc Dang <dhdang@apm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-02-12 19:39:26 -08:00
mailbox: Add Broadcom PDC mailbox driver The Broadcom PDC mailbox driver is a mailbox controller that manages data transfers to and from one or more offload engines. Signed-off-by: Rob Rice <rob.rice@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-06-30 15:59:23 -04:00
mailbox: bcm-pdc: Add Northstar Plus support to PDC driver Adds support for Northstar Plus (NS+) products to the PDC mailbox driver. The PDC driver was originally written to support the PDC ring manager in the Northstar2 (64-bit) device. The NS+ (32 bit device) uses an almost identical ring manager, though with a different name. We just need to check for the type of hardware in use, in order to write the appropriate interrupt configuration register. Also updated DMA width to be correct for both NS+ and NS2. Tested on NS+ and NS2. Signed-off-by: Steve Lin <steven.lin1@broadcom.com> Acked-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2017-02-23 09:49:50 -05:00
mailbox: Add Broadcom PDC mailbox driver The Broadcom PDC mailbox driver is a mailbox controller that manages data transfers to and from one or more offload engines. Signed-off-by: Rob Rice <rob.rice@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-06-30 15:59:23 -04:00
mailbox: bcm-pdc: Add Northstar Plus support to PDC driver Adds support for Northstar Plus (NS+) products to the PDC mailbox driver. The PDC driver was originally written to support the PDC ring manager in the Northstar2 (64-bit) device. The NS+ (32 bit device) uses an almost identical ring manager, though with a different name. We just need to check for the type of hardware in use, in order to write the appropriate interrupt configuration register. Also updated DMA width to be correct for both NS+ and NS2. Tested on NS+ and NS2. Signed-off-by: Steve Lin <steven.lin1@broadcom.com> Acked-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2017-02-23 09:49:50 -05:00
mailbox: Add Broadcom PDC mailbox driver The Broadcom PDC mailbox driver is a mailbox controller that manages data transfers to and from one or more offload engines. Signed-off-by: Rob Rice <rob.rice@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-06-30 15:59:23 -04:00
mailbox: bcm-pdc: Add Northstar Plus support to PDC driver Adds support for Northstar Plus (NS+) products to the PDC mailbox driver. The PDC driver was originally written to support the PDC ring manager in the Northstar2 (64-bit) device. The NS+ (32 bit device) uses an almost identical ring manager, though with a different name. We just need to check for the type of hardware in use, in order to write the appropriate interrupt configuration register. Also updated DMA width to be correct for both NS+ and NS2. Tested on NS+ and NS2. Signed-off-by: Steve Lin <steven.lin1@broadcom.com> Acked-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2017-02-23 09:49:50 -05:00
mailbox: Add driver for Broadcom FlexRM ring manager Some of the Broadcom iProc SoCs have FlexRM ring manager which provides a ring-based programming interface to various offload engines (e.g. RAID, Crypto, etc). This patch adds a common mailbox driver for Broadcom FlexRM ring manager which can be shared by various offload engine drivers (implemented as mailbox clients). Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Pramod KUMAR <pramod.kumar@broadcom.com> Signed-off-by: Anup Patel <anup.patel@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2017-03-15 12:10:00 +05:30
mailbox: Remove depends on COMPILE_TEST for BCM_FLEXRM_MBOX The Broadcom FlexRM mailbox driver uses platform MSI support but not all ARCHs provide asm/msi.h. Due to this, we get compilation error in Broadcom FlexRM mailbox driver via linux/msi.h on ARCHs which lack asm/msi.h. This patch removes "depends on COMPILE_TEST" for Kconfig option BCM_FLEXRM_MBOX so that Broadcom FlexRM mailbox driver is only compiled for ARM64. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2017-03-29 11:00:55 +05:30
mailbox: bcm-flexrm-mailbox: add depends on ARCH_BCM_IPROC The Broadcom FlexRM Mailbox is only present in the Broadcom IPROC SoCs. Add depends on ARCH_BCM_IPROC to BCM_FLEXRX_MBOX. Signed-off-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2017-10-03 10:51:50 +05:30
mailbox: Add driver for Broadcom FlexRM ring manager Some of the Broadcom iProc SoCs have FlexRM ring manager which provides a ring-based programming interface to various offload engines (e.g. RAID, Crypto, etc). This patch adds a common mailbox driver for Broadcom FlexRM ring manager which can be shared by various offload engine drivers (implemented as mailbox clients). Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Pramod KUMAR <pramod.kumar@broadcom.com> Signed-off-by: Anup Patel <anup.patel@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2017-03-15 12:10:00 +05:30
mailbox: Build Broadcom FlexRM driver as loadable module for iProc SOCs By default, we build Broadcom FlexRM driver as loadable module for iProc SOCs so that kernel image is little smaller and we load FlexRM driver only when required. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2017-10-03 10:51:52 +05:30
mailbox: Add driver for Broadcom FlexRM ring manager Some of the Broadcom iProc SoCs have FlexRM ring manager which provides a ring-based programming interface to various offload engines (e.g. RAID, Crypto, etc). This patch adds a common mailbox driver for Broadcom FlexRM ring manager which can be shared by various offload engine drivers (implemented as mailbox clients). Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Pramod KUMAR <pramod.kumar@broadcom.com> Signed-off-by: Anup Patel <anup.patel@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2017-03-15 12:10:00 +05:30
mailbox: add STMicroelectronics STM32 IPCC driver The STMicroelectronics STM32 Inter-Processor Communication Controller (IPCC) is used for communicating data between two processors. It provides a non blocking signaling mechanism to post and retrieve communication data in an atomic way. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-05-31 10:27:25 +02:00
mailbox: stm32-ipcc: add COMPILE_TEST dependency This allows compiling the driver on architectures where the hardware is not available. Most other mailbox drivers support this as well. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-11-01 16:42:29 +01:00
mailbox: add STMicroelectronics STM32 IPCC driver The STMicroelectronics STM32 Inter-Processor Communication Controller (IPCC) is used for communicating data between two processors. It provides a non blocking signaling mechanism to post and retrieve communication data in an atomic way. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-05-31 10:27:25 +02:00
mailbox: mediatek: Add Mediatek CMDQ driver This patch is first version of Mediatek Command Queue(CMDQ) driver. The CMDQ is used to help write registers with critical time limitation, such as updating display configuration during the vblank. It controls Global Command Engine (GCE) hardware to achieve this requirement. Currently, CMDQ only supports display related hardwares, but we expect it can be extended to other hardwares for future requirements. Signed-off-by: Houlong Wei <houlong.wei@mediatek.com> Signed-off-by: HS Liao <hs.liao@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-07-25 09:26:40 +08:00
mailbox: mediatek: add support for adsp mailbox controller This patch is to for MediaTek ADSP IPC mailbox controller driver It is used to send short messages between processors with adsp Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Tzung-Bi Shih <tzungbi@google.com> Reviewed-by: YC Hung <yc.hung@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-02-25 21:24:27 +08:00
mailbox: mediatek: Add Mediatek CMDQ driver This patch is first version of Mediatek Command Queue(CMDQ) driver. The CMDQ is used to help write registers with critical time limitation, such as updating display configuration during the vblank. It controls Global Command Engine (GCE) hardware to achieve this requirement. Currently, CMDQ only supports display related hardwares, but we expect it can be extended to other hardwares for future requirements. Signed-off-by: Houlong Wei <houlong.wei@mediatek.com> Signed-off-by: HS Liao <hs.liao@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-07-25 09:26:40 +08:00
mailbox: ZynqMP IPI mailbox controller This patch is to introduce ZynqMP IPI mailbox controller driver to use the ZynqMP IPI block as mailboxes. Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-02-21 16:36:33 -08:00
mailbox: sun6i-msgbox: Add a new mailbox driver Allwinner sun6i, sun8i, sun9i, and sun50i SoCs contain a hardware message box used for communication between the ARM CPUs and the ARISC management coprocessor. This mailbox contains 8 unidirectional 4-message FIFOs. Add a driver for it, so it can be used with the Linux mailbox framework. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-02-22 22:08:49 -06:00
mailbox: sprd: Add Spreadtrum mailbox driver The Spreadtrum mailbox controller supports 8 channels to communicate with MCUs, and it contains 2 different parts: inbox and outbox, which are used to send and receive messages by IRQ mode. Signed-off-by: Baolin Wang <baolin.wang@unisoc.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-22 21:31:09 +08:00
mailbox: Add support for Qualcomm IPCC Add support for the Inter-Processor Communication Controller (IPCC) block from Qualcomm that coordinates the interrupts (inbound & outbound) for Multiprocessor (MPROC), COMPUTE-Level0 (COMPUTE-L0) & COMPUTE-Level1 (COMPUTE-L1) protocols for the Application Processor Subsystem (APSS). This driver is modeled as an irqchip+mailbox driver. The irqchip part helps in receiving the interrupts from the IPCC clients such as modems, DSPs, PCI-E etc... and forwards them to respective entities in APSS. On the other hand, the mailbox part is used to send interrupts to the IPCC clients from the entities of APSS. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> [mani: moved to mailbox, added static mbox channels and cleanups] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-30 18:15:12 -05:00
mailbox: qcom-ipcc: Enable loading QCOM_IPCC as a module This patch enables the qcom_ipcc driver to be loaded as a module. IPCC is fairly core to system, so as such it should never be unloaded. It registers as a mailbox + irq controller and the irq controller drivers in kernel are not supposed to be unloaded as they don't have the visibility over the clients consuming the irqs. Hence adding supress_bind_attrs to disable bind/unbind via sysfs. Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-07-16 13:19:46 +05:30
mailbox: Add support for Qualcomm IPCC Add support for the Inter-Processor Communication Controller (IPCC) block from Qualcomm that coordinates the interrupts (inbound & outbound) for Multiprocessor (MPROC), COMPUTE-Level0 (COMPUTE-L0) & COMPUTE-Level1 (COMPUTE-L1) protocols for the Application Processor Subsystem (APSS). This driver is modeled as an irqchip+mailbox driver. The irqchip part helps in receiving the interrupts from the IPCC clients such as modems, DSPs, PCI-E etc... and forwards them to respective entities in APSS. On the other hand, the mailbox part is used to send interrupts to the IPCC clients from the entities of APSS. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> [mani: moved to mailbox, added static mbox channels and cleanups] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-30 18:15:12 -05:00
ARM / highbank: add support for pl320 IPC The pl320 IPC allows for interprocessor communication between the highbank A9 and the EnergyCore Management Engine. The pl320 implements a straightforward mailbox protocol. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-01-28 16:13:14 +00:00