2019-05-27 08:55:05 +02:00
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2008-06-23 19:50:15 +08:00
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2011-07-15 11:21:38 +08:00
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2008-06-23 19:50:15 +08:00
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2026-03-30 12:28:18 +02:00
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2008-06-23 19:50:15 +08:00
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2023-07-14 11:44:18 -06:00
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2013-09-17 14:28:33 -05:00
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2023-07-14 11:44:18 -06:00
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2008-06-23 19:50:15 +08:00
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 17:04:11 +09:00
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2008-06-23 19:50:15 +08:00
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2019-08-15 12:01:05 +03:00
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2020-11-12 21:20:21 -08:00
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2010-05-19 19:20:36 +10:00
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2015-05-11 17:47:48 +08:00
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2008-06-23 19:50:15 +08:00
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2019-11-09 18:09:49 +01:00
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2010-05-19 19:19:33 +10:00
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2009-03-29 15:52:32 +08:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:07 +02:00
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2017-10-06 15:04:57 +02:00
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2009-08-13 11:51:51 +10:00
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2015-04-17 16:31:53 +02:00
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2017-10-06 15:04:57 +02:00
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2015-04-17 16:32:07 +02:00
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2017-10-06 15:04:57 +02:00
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2009-08-13 11:51:51 +10:00
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2016-04-19 20:33:48 +03:00
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2015-04-17 16:32:07 +02:00
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2017-10-06 15:04:57 +02:00
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2015-04-17 16:32:07 +02:00
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2017-10-06 15:04:57 +02:00
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2015-04-17 16:32:07 +02:00
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2015-04-17 16:31:59 +02:00
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2015-04-17 16:32:07 +02:00
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2015-04-17 16:31:59 +02:00
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2015-04-17 16:32:07 +02:00
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2015-04-17 16:31:59 +02:00
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2016-06-06 13:20:34 +02:00
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2015-04-17 16:31:55 +02:00
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2015-04-17 16:32:07 +02:00
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2016-06-06 13:20:34 +02:00
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2015-04-17 16:31:55 +02:00
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2008-06-23 19:50:15 +08:00
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2018-02-26 17:40:06 +01:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:31:53 +02:00
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2015-05-11 20:04:56 +03:00
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2008-06-23 19:50:15 +08:00
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2018-02-26 17:40:06 +01:00
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2009-08-13 11:51:51 +10:00
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2018-02-26 17:40:06 +01:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:31:53 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:07 +02:00
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2015-04-17 16:31:53 +02:00
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2015-04-17 16:32:07 +02:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:51:51 +10:00
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2011-11-21 16:13:27 +08:00
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2009-08-13 11:51:51 +10:00
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2017-10-06 15:05:06 +02:00
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2008-06-23 19:50:15 +08:00
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2008-10-12 20:33:14 +08:00
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2011-11-21 16:13:27 +08:00
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2008-10-12 20:33:14 +08:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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2011-11-21 16:13:27 +08:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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2011-12-12 14:59:11 -06:00
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2011-11-21 16:13:27 +08:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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2008-10-12 20:33:14 +08:00
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2015-04-17 16:32:11 +02:00
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2008-10-12 20:33:14 +08:00
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2008-06-23 19:50:15 +08:00
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2011-07-15 11:21:38 +08:00
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2008-06-23 19:50:15 +08:00
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2019-05-21 13:34:20 +00:00
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2008-06-23 19:50:15 +08:00
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2011-07-15 11:21:38 +08:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:09 +02:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:50:38 +10:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:50:38 +10:00
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2008-07-17 20:16:40 +08:00
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2009-08-13 11:50:38 +10:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:50:38 +10:00
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2008-07-17 20:16:40 +08:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:09 +02:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:50:38 +10:00
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2008-06-23 19:50:15 +08:00
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2011-11-21 16:13:27 +08:00
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2010-09-23 15:56:38 +08:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:50:38 +10:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - fix hash on SEC1.
On SEC1, hash provides wrong result when performing hashing in several
steps with input data SG list has more than one element. This was
detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[ 44.185947] alg: hash: md5-talitos test failed (wrong result) on test vector 6, cfg="random: may_sleep use_finup src_divs=[<reimport>25.88%@+8063, <flush>24.19%@+9588, 28.63%@+16333, <reimport>4.60%@+6756, 16.70%@+16281] dst_divs=[71.61%@alignmask+16361, 14.36%@+7756, 14.3%@+"
[ 44.325122] alg: hash: sha1-talitos test failed (wrong result) on test vector 3, cfg="random: inplace use_final src_divs=[<flush,nosimd>16.56%@+16378, <reimport>52.0%@+16329, 21.42%@alignmask+16380, 10.2%@alignmask+16380] iv_offset=39"
[ 44.493500] alg: hash: sha224-talitos test failed (wrong result) on test vector 4, cfg="random: use_final nosimd src_divs=[<reimport>52.27%@+7401, <reimport>17.34%@+16285, <flush>17.71%@+26, 12.68%@+10644] iv_offset=43"
[ 44.673262] alg: hash: sha256-talitos test failed (wrong result) on test vector 4, cfg="random: may_sleep use_finup src_divs=[<reimport>60.6%@+12790, 17.86%@+1329, <reimport>12.64%@alignmask+16300, 8.29%@+15, 0.40%@+13506, <reimport>0.51%@+16322, <reimport>0.24%@+16339] dst_divs"
This is due to two issues:
- We have an overlap between the buffer used for copying the input
data (SEC1 doesn't do scatter/gather) and the chained descriptor.
- Data copy is wrong when the previous hash left less than one
blocksize of data to hash, implying a complement of the previous
block with a few bytes from the new request.
Fix it by:
- Moving the second descriptor after the buffer, as moving the buffer
after the descriptor would make it more complex for other cipher
operations (AEAD, ABLKCIPHER)
- Skip the bytes taken from the new request to complete the previous
one by moving the SG list forward.
Fixes: 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash on SEC1")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-06-24 07:20:16 +00:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:09 +02:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:50:38 +10:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:50:38 +10:00
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2015-04-17 16:32:09 +02:00
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2009-08-13 11:50:38 +10:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - fix hash on SEC1.
On SEC1, hash provides wrong result when performing hashing in several
steps with input data SG list has more than one element. This was
detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[ 44.185947] alg: hash: md5-talitos test failed (wrong result) on test vector 6, cfg="random: may_sleep use_finup src_divs=[<reimport>25.88%@+8063, <flush>24.19%@+9588, 28.63%@+16333, <reimport>4.60%@+6756, 16.70%@+16281] dst_divs=[71.61%@alignmask+16361, 14.36%@+7756, 14.3%@+"
[ 44.325122] alg: hash: sha1-talitos test failed (wrong result) on test vector 3, cfg="random: inplace use_final src_divs=[<flush,nosimd>16.56%@+16378, <reimport>52.0%@+16329, 21.42%@alignmask+16380, 10.2%@alignmask+16380] iv_offset=39"
[ 44.493500] alg: hash: sha224-talitos test failed (wrong result) on test vector 4, cfg="random: use_final nosimd src_divs=[<reimport>52.27%@+7401, <reimport>17.34%@+16285, <flush>17.71%@+26, 12.68%@+10644] iv_offset=43"
[ 44.673262] alg: hash: sha256-talitos test failed (wrong result) on test vector 4, cfg="random: may_sleep use_finup src_divs=[<reimport>60.6%@+12790, 17.86%@+1329, <reimport>12.64%@alignmask+16300, 8.29%@+15, 0.40%@+13506, <reimport>0.51%@+16322, <reimport>0.24%@+16339] dst_divs"
This is due to two issues:
- We have an overlap between the buffer used for copying the input
data (SEC1 doesn't do scatter/gather) and the chained descriptor.
- Data copy is wrong when the previous hash left less than one
blocksize of data to hash, implying a complement of the previous
block with a few bytes from the new request.
Fix it by:
- Moving the second descriptor after the buffer, as moving the buffer
after the descriptor would make it more complex for other cipher
operations (AEAD, ABLKCIPHER)
- Skip the bytes taken from the new request to complete the previous
one by moving the SG list forward.
Fixes: 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash on SEC1")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-06-24 07:20:16 +00:00
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2015-04-17 16:32:09 +02:00
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2008-06-23 19:50:15 +08:00
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2008-12-20 17:09:25 +11:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:09 +02:00
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2009-03-29 15:53:23 +08:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:50:38 +10:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:50:38 +10:00
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2008-07-17 20:16:40 +08:00
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2009-08-13 11:50:38 +10:00
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2008-07-17 20:16:40 +08:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:50:38 +10:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:50:38 +10:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2017-10-06 15:04:55 +02:00
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|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2011-11-21 16:13:27 +08:00
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2012-03-30 17:49:53 +03:00
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2011-11-21 16:13:27 +08:00
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2012-03-30 17:49:53 +03:00
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2011-11-21 16:13:27 +08:00
|
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|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
|
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|
2012-03-30 17:49:53 +03:00
|
|
|
|
2008-06-23 19:50:15 +08:00
|
|
|
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
|
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2017-10-06 15:04:55 +02:00
|
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|
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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2020-10-08 09:34:56 +00:00
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2008-06-23 19:50:15 +08:00
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2013-11-13 12:20:37 +02:00
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2008-06-23 19:50:15 +08:00
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2013-11-13 12:20:37 +02:00
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2008-06-23 19:50:15 +08:00
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2013-11-13 12:20:37 +02:00
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2017-10-06 15:05:06 +02:00
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2020-10-08 09:34:55 +00:00
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2013-11-13 12:20:37 +02:00
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2008-06-23 19:50:15 +08:00
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2011-10-21 15:20:28 +02:00
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2008-06-23 19:50:15 +08:00
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2020-10-08 09:34:55 +00:00
|
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|
crypto: talitos - fix hash on SEC1.
On SEC1, hash provides wrong result when performing hashing in several
steps with input data SG list has more than one element. This was
detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[ 44.185947] alg: hash: md5-talitos test failed (wrong result) on test vector 6, cfg="random: may_sleep use_finup src_divs=[<reimport>25.88%@+8063, <flush>24.19%@+9588, 28.63%@+16333, <reimport>4.60%@+6756, 16.70%@+16281] dst_divs=[71.61%@alignmask+16361, 14.36%@+7756, 14.3%@+"
[ 44.325122] alg: hash: sha1-talitos test failed (wrong result) on test vector 3, cfg="random: inplace use_final src_divs=[<flush,nosimd>16.56%@+16378, <reimport>52.0%@+16329, 21.42%@alignmask+16380, 10.2%@alignmask+16380] iv_offset=39"
[ 44.493500] alg: hash: sha224-talitos test failed (wrong result) on test vector 4, cfg="random: use_final nosimd src_divs=[<reimport>52.27%@+7401, <reimport>17.34%@+16285, <flush>17.71%@+26, 12.68%@+10644] iv_offset=43"
[ 44.673262] alg: hash: sha256-talitos test failed (wrong result) on test vector 4, cfg="random: may_sleep use_finup src_divs=[<reimport>60.6%@+12790, 17.86%@+1329, <reimport>12.64%@alignmask+16300, 8.29%@+15, 0.40%@+13506, <reimport>0.51%@+16322, <reimport>0.24%@+16339] dst_divs"
This is due to two issues:
- We have an overlap between the buffer used for copying the input
data (SEC1 doesn't do scatter/gather) and the chained descriptor.
- Data copy is wrong when the previous hash left less than one
blocksize of data to hash, implying a complement of the previous
block with a few bytes from the new request.
Fix it by:
- Moving the second descriptor after the buffer, as moving the buffer
after the descriptor would make it more complex for other cipher
operations (AEAD, ABLKCIPHER)
- Skip the bytes taken from the new request to complete the previous
one by moving the SG list forward.
Fixes: 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash on SEC1")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-06-24 07:20:16 +00:00
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2017-10-06 15:05:06 +02:00
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2013-11-13 12:20:37 +02:00
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2008-06-23 19:50:15 +08:00
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2020-10-08 09:34:56 +00:00
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2008-06-23 19:50:15 +08:00
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2011-10-21 15:20:28 +02:00
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2020-10-08 09:34:56 +00:00
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2011-10-21 15:20:28 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2011-10-21 15:20:28 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2011-11-21 16:13:27 +08:00
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2008-06-23 19:50:15 +08:00
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2011-12-12 14:59:12 -06:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2015-05-11 20:04:56 +03:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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2011-11-21 16:13:27 +08:00
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2008-06-23 19:50:15 +08:00
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2016-11-01 20:14:04 -06:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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|
2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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2011-10-21 15:20:28 +02:00
|
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|
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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2011-11-21 16:13:27 +08:00
|
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|
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2011-11-21 16:13:27 +08:00
|
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|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2011-11-21 16:13:27 +08:00
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2012-03-30 17:49:53 +03:00
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2011-11-21 16:13:27 +08:00
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2012-03-30 17:49:53 +03:00
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2011-11-21 16:13:27 +08:00
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2012-03-30 17:49:53 +03:00
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2011-11-21 16:13:27 +08:00
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2012-03-30 17:49:53 +03:00
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2011-11-21 16:13:27 +08:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:11 +02:00
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2008-06-23 19:50:15 +08:00
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2015-08-05 16:52:08 -05:00
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2008-06-23 19:50:15 +08:00
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2020-09-27 21:12:23 +02:00
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2008-06-23 19:50:15 +08:00
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2015-08-05 16:52:08 -05:00
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2008-06-23 19:50:15 +08:00
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2015-08-05 16:52:08 -05:00
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2008-06-23 19:50:15 +08:00
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2015-08-05 16:52:08 -05:00
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2008-06-23 19:50:15 +08:00
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2016-06-06 13:20:46 +02:00
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2019-06-12 05:49:50 +00:00
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2017-05-02 09:38:35 -04:00
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2019-05-21 13:34:09 +00:00
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2008-07-10 18:29:18 +08:00
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2008-07-03 19:08:46 +08:00
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2008-06-23 19:50:15 +08:00
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2011-07-15 11:21:38 +08:00
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2008-06-23 19:50:15 +08:00
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2008-07-03 19:08:46 +08:00
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2017-10-06 15:05:02 +02:00
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2008-06-23 19:50:15 +08:00
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2010-05-19 19:20:36 +10:00
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2010-05-19 19:21:53 +10:00
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2010-05-19 19:20:36 +10:00
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2017-10-06 15:05:08 +02:00
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2010-05-19 19:21:53 +10:00
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2026-03-30 12:28:19 +02:00
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2026-03-30 12:28:18 +02:00
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2010-05-19 19:20:36 +10:00
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2015-05-11 20:04:56 +03:00
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2010-05-19 19:20:36 +10:00
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2026-03-30 12:28:18 +02:00
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2010-05-19 19:20:36 +10:00
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2016-04-21 19:24:55 +03:00
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2026-03-30 12:28:19 +02:00
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2016-04-21 19:24:55 +03:00
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2009-03-29 15:50:50 +08:00
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2008-06-23 19:50:15 +08:00
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2017-10-06 15:05:02 +02:00
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2013-10-15 13:49:34 +02:00
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2008-06-23 19:50:15 +08:00
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2013-10-15 13:49:34 +02:00
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2008-06-23 19:50:15 +08:00
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2013-10-15 13:49:34 +02:00
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2008-06-23 19:50:15 +08:00
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2017-10-06 15:05:02 +02:00
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2013-10-15 13:49:34 +02:00
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2008-06-23 19:50:15 +08:00
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2013-10-15 13:49:34 +02:00
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2017-10-06 15:05:02 +02:00
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2008-06-23 19:50:15 +08:00
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2018-03-23 12:42:24 +02:00
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2008-06-23 19:50:15 +08:00
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2018-03-23 12:42:24 +02:00
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2008-06-23 19:50:15 +08:00
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2019-04-11 16:51:21 +08:00
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crypto: remove CRYPTO_TFM_RES_BAD_KEY_LEN
The CRYPTO_TFM_RES_BAD_KEY_LEN flag was apparently meant as a way to
make the ->setkey() functions provide more information about errors.
However, no one actually checks for this flag, which makes it pointless.
Also, many algorithms fail to set this flag when given a bad length key.
Reviewing just the generic implementations, this is the case for
aes-fixed-time, cbcmac, echainiv, nhpoly1305, pcrypt, rfc3686, rfc4309,
rfc7539, rfc7539esp, salsa20, seqiv, and xcbc. But there are probably
many more in arch/*/crypto/ and drivers/crypto/.
Some algorithms can even set this flag when the key is the correct
length. For example, authenc and authencesn set it when the key payload
is malformed in any way (not just a bad length), the atmel-sha and ccree
drivers can set it if a memory allocation fails, and the chelsio driver
sets it for bad auth tag lengths, not just bad key lengths.
So even if someone actually wanted to start checking this flag (which
seems unlikely, since it's been unused for a long time), there would be
a lot of work needed to get it working correctly. But it would probably
be much better to go back to the drawing board and just define different
return values, like -EINVAL if the key is invalid for the algorithm vs.
-EKEYREJECTED if the key was rejected by a policy like "no weak keys".
That would be much simpler, less error-prone, and easier to test.
So just remove this flag.
Signed-off-by: Eric Biggers <ebiggers@google.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-12-30 21:19:36 -06:00
|
|
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|
2019-04-11 16:51:21 +08:00
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|
crypto: remove CRYPTO_TFM_RES_BAD_KEY_LEN
The CRYPTO_TFM_RES_BAD_KEY_LEN flag was apparently meant as a way to
make the ->setkey() functions provide more information about errors.
However, no one actually checks for this flag, which makes it pointless.
Also, many algorithms fail to set this flag when given a bad length key.
Reviewing just the generic implementations, this is the case for
aes-fixed-time, cbcmac, echainiv, nhpoly1305, pcrypt, rfc3686, rfc4309,
rfc7539, rfc7539esp, salsa20, seqiv, and xcbc. But there are probably
many more in arch/*/crypto/ and drivers/crypto/.
Some algorithms can even set this flag when the key is the correct
length. For example, authenc and authencesn set it when the key payload
is malformed in any way (not just a bad length), the atmel-sha and ccree
drivers can set it if a memory allocation fails, and the chelsio driver
sets it for bad auth tag lengths, not just bad key lengths.
So even if someone actually wanted to start checking this flag (which
seems unlikely, since it's been unused for a long time), there would be
a lot of work needed to get it working correctly. But it would probably
be much better to go back to the drawing board and just define different
return values, like -EINVAL if the key is invalid for the algorithm vs.
-EKEYREJECTED if the key was rejected by a policy like "no weak keys".
That would be much simpler, less error-prone, and easier to test.
So just remove this flag.
Signed-off-by: Eric Biggers <ebiggers@google.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-12-30 21:19:36 -06:00
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2019-04-11 16:51:21 +08:00
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2019-08-15 12:01:05 +03:00
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2019-04-11 16:51:21 +08:00
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2009-03-29 15:52:32 +08:00
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2016-06-06 13:20:38 +02:00
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2016-06-06 13:20:36 +02:00
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2016-06-06 13:20:38 +02:00
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2016-06-06 13:20:36 +02:00
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2016-06-06 13:20:38 +02:00
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2016-06-06 13:20:36 +02:00
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2008-06-23 19:50:15 +08:00
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2009-03-29 15:50:50 +08:00
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2019-05-21 13:34:14 +00:00
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2008-06-23 19:50:15 +08:00
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2016-06-06 13:20:40 +02:00
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2019-05-21 13:34:14 +00:00
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2017-10-06 15:04:59 +02:00
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2016-06-06 13:20:40 +02:00
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2017-10-06 15:04:59 +02:00
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2016-06-06 13:20:40 +02:00
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2017-10-06 15:04:59 +02:00
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2008-06-23 19:50:15 +08:00
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2019-05-21 13:34:19 +00:00
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2008-06-23 19:50:15 +08:00
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2016-06-06 13:20:40 +02:00
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2017-10-06 15:04:59 +02:00
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2016-06-06 13:20:40 +02:00
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2019-05-21 13:34:14 +00:00
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2016-06-06 13:20:40 +02:00
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2008-06-23 19:50:15 +08:00
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2017-10-06 15:05:02 +02:00
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2009-03-29 15:53:59 +08:00
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2008-06-23 19:50:15 +08:00
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2009-03-29 15:53:59 +08:00
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2019-05-21 13:34:14 +00:00
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2008-06-23 19:50:15 +08:00
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2017-10-06 15:05:02 +02:00
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2008-06-23 19:50:15 +08:00
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2008-10-12 20:33:14 +08:00
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2009-03-29 15:53:23 +08:00
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2008-06-23 19:50:15 +08:00
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2015-07-30 17:53:22 +08:00
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2009-03-29 15:53:59 +08:00
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2015-07-30 17:53:22 +08:00
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2008-06-23 19:50:15 +08:00
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2009-03-29 15:53:59 +08:00
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2015-07-30 17:53:22 +08:00
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2008-06-23 19:50:15 +08:00
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2008-10-12 20:33:14 +08:00
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2009-03-29 15:53:23 +08:00
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2008-10-12 20:33:14 +08:00
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2009-03-29 15:53:59 +08:00
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2008-10-12 20:33:14 +08:00
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2008-10-12 20:33:14 +08:00
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2009-03-29 15:53:23 +08:00
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2008-10-12 20:33:14 +08:00
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2008-06-23 19:50:15 +08:00
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2015-07-30 17:53:22 +08:00
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2019-05-21 13:34:19 +00:00
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2021-01-20 18:57:24 +00:00
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2008-06-23 19:50:15 +08:00
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2019-05-21 13:34:19 +00:00
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2015-07-30 17:53:22 +08:00
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2019-05-21 13:34:19 +00:00
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2021-01-20 18:57:24 +00:00
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2008-07-03 19:08:46 +08:00
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2015-07-30 17:53:22 +08:00
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2015-07-30 17:53:22 +08:00
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2021-01-20 18:57:24 +00:00
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2016-06-06 13:20:34 +02:00
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2015-07-30 17:53:22 +08:00
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2019-05-21 13:34:19 +00:00
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2015-07-30 17:53:22 +08:00
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2015-01-20 10:06:16 +02:00
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2008-06-23 19:50:15 +08:00
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2015-07-30 17:53:22 +08:00
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2016-06-06 13:20:34 +02:00
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2019-05-21 13:34:19 +00:00
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2008-07-03 19:08:46 +08:00
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2015-07-30 17:53:22 +08:00
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2018-03-22 10:57:01 +01:00
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2019-05-21 13:34:19 +00:00
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2021-01-20 18:57:24 +00:00
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2016-06-06 13:20:36 +02:00
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2021-01-20 18:57:24 +00:00
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2016-06-06 13:20:36 +02:00
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2018-01-26 17:09:59 +01:00
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2018-03-22 10:57:01 +01:00
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2019-05-21 13:34:19 +00:00
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2021-01-20 18:57:24 +00:00
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2016-06-06 13:20:38 +02:00
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2016-06-06 13:20:36 +02:00
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2016-06-06 13:20:38 +02:00
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2021-01-20 18:57:24 +00:00
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2016-06-06 13:20:38 +02:00
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2021-01-20 18:57:24 +00:00
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2016-06-06 13:20:38 +02:00
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2021-01-20 18:57:24 +00:00
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2016-06-06 13:20:38 +02:00
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2016-06-06 13:20:36 +02:00
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2018-03-22 10:57:01 +01:00
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2021-01-20 18:57:24 +00:00
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2018-03-22 10:57:01 +01:00
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2008-06-23 19:50:15 +08:00
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2009-03-29 15:50:50 +08:00
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2019-05-21 13:34:14 +00:00
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2015-07-30 17:53:22 +08:00
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2008-06-23 19:50:15 +08:00
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2015-07-30 17:53:22 +08:00
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2008-06-23 19:50:15 +08:00
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2019-05-21 13:34:14 +00:00
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2009-08-13 11:49:06 +10:00
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2015-07-30 17:53:22 +08:00
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2008-07-17 20:20:06 +08:00
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2018-03-22 10:57:01 +01:00
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2016-06-06 13:20:40 +02:00
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2017-10-06 15:04:59 +02:00
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2019-05-21 13:34:19 +00:00
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2017-10-06 15:05:02 +02:00
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2012-08-02 17:16:40 +03:00
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2016-06-06 13:20:40 +02:00
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2016-04-19 20:33:48 +03:00
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2016-06-06 13:20:40 +02:00
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2016-04-19 20:33:48 +03:00
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2016-06-06 13:20:40 +02:00
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2012-08-02 17:16:40 +03:00
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2008-06-23 19:50:15 +08:00
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2008-06-23 19:50:15 +08:00
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2018-03-22 10:57:01 +01:00
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2008-06-23 19:50:15 +08:00
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2018-03-22 10:57:01 +01:00
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2019-05-21 13:34:19 +00:00
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2021-01-20 18:57:24 +00:00
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2016-06-06 13:20:40 +02:00
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2008-06-23 19:50:15 +08:00
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2016-06-06 13:20:40 +02:00
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2008-06-23 19:50:15 +08:00
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2019-05-21 13:34:19 +00:00
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2021-01-20 18:57:24 +00:00
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2019-05-21 13:34:19 +00:00
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2008-06-23 19:50:15 +08:00
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2019-05-21 13:34:19 +00:00
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2016-06-06 13:20:40 +02:00
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2019-05-21 13:34:19 +00:00
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2016-06-06 13:20:40 +02:00
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2017-10-06 15:04:59 +02:00
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2019-05-21 13:34:19 +00:00
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2016-06-06 13:20:40 +02:00
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2008-06-23 19:50:15 +08:00
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2017-10-06 15:04:59 +02:00
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2016-06-06 13:20:40 +02:00
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2008-06-23 19:50:15 +08:00
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2011-07-15 11:21:38 +08:00
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2008-07-17 20:20:06 +08:00
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2019-05-21 13:34:14 +00:00
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2008-07-17 20:20:06 +08:00
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2008-06-23 19:50:15 +08:00
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2009-03-29 15:50:50 +08:00
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2008-06-23 19:50:15 +08:00
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2009-03-29 15:52:32 +08:00
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2012-08-02 17:16:40 +03:00
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2009-03-29 15:52:32 +08:00
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2012-08-02 17:16:40 +03:00
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2009-03-29 15:52:32 +08:00
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2013-11-28 15:11:17 +02:00
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2008-06-23 19:50:15 +08:00
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2009-03-29 15:50:50 +08:00
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2016-06-06 13:20:38 +02:00
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2012-08-02 17:16:40 +03:00
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2009-03-29 15:52:32 +08:00
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2008-07-17 20:19:18 +08:00
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2015-04-17 16:32:15 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:15 +02:00
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2009-03-29 15:52:32 +08:00
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2008-06-23 19:50:15 +08:00
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2013-11-28 15:11:17 +02:00
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2016-06-06 13:20:38 +02:00
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2015-11-04 21:13:34 +01:00
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2019-01-08 06:56:46 +00:00
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2015-11-04 21:13:34 +01:00
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2013-11-28 15:11:17 +02:00
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2016-06-06 13:20:38 +02:00
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2013-11-28 15:11:17 +02:00
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2016-06-06 13:20:38 +02:00
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2015-11-04 21:13:34 +01:00
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2019-01-08 06:56:46 +00:00
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2015-11-04 21:13:34 +01:00
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2013-11-28 15:11:17 +02:00
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2016-06-06 13:20:38 +02:00
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2015-11-04 21:13:34 +01:00
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2019-01-08 06:56:46 +00:00
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2015-11-04 21:13:34 +01:00
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2013-11-28 15:11:17 +02:00
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2008-06-23 19:50:15 +08:00
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2015-07-30 17:53:22 +08:00
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2008-06-23 19:50:15 +08:00
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2009-03-29 15:50:50 +08:00
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2019-05-21 13:34:19 +00:00
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2015-04-17 16:32:15 +02:00
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2016-06-06 13:20:38 +02:00
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2019-05-21 13:34:19 +00:00
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2015-04-17 16:32:15 +02:00
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2015-07-30 17:53:22 +08:00
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2019-05-21 13:34:19 +00:00
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2008-06-23 19:50:15 +08:00
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2017-10-06 15:05:06 +02:00
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2019-01-08 06:56:48 +00:00
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2017-10-06 15:05:06 +02:00
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2022-12-30 15:31:33 +08:00
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2019-01-08 06:56:46 +00:00
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2019-01-08 06:56:48 +00:00
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2019-01-08 06:56:46 +00:00
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2019-01-08 06:56:48 +00:00
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2017-10-06 15:04:45 +02:00
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2008-06-23 19:50:15 +08:00
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2012-08-02 17:16:40 +03:00
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2008-06-23 19:50:15 +08:00
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crypto: talitos - fix hash on SEC1.
On SEC1, hash provides wrong result when performing hashing in several
steps with input data SG list has more than one element. This was
detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[ 44.185947] alg: hash: md5-talitos test failed (wrong result) on test vector 6, cfg="random: may_sleep use_finup src_divs=[<reimport>25.88%@+8063, <flush>24.19%@+9588, 28.63%@+16333, <reimport>4.60%@+6756, 16.70%@+16281] dst_divs=[71.61%@alignmask+16361, 14.36%@+7756, 14.3%@+"
[ 44.325122] alg: hash: sha1-talitos test failed (wrong result) on test vector 3, cfg="random: inplace use_final src_divs=[<flush,nosimd>16.56%@+16378, <reimport>52.0%@+16329, 21.42%@alignmask+16380, 10.2%@alignmask+16380] iv_offset=39"
[ 44.493500] alg: hash: sha224-talitos test failed (wrong result) on test vector 4, cfg="random: use_final nosimd src_divs=[<reimport>52.27%@+7401, <reimport>17.34%@+16285, <flush>17.71%@+26, 12.68%@+10644] iv_offset=43"
[ 44.673262] alg: hash: sha256-talitos test failed (wrong result) on test vector 4, cfg="random: may_sleep use_finup src_divs=[<reimport>60.6%@+12790, 17.86%@+1329, <reimport>12.64%@alignmask+16300, 8.29%@+15, 0.40%@+13506, <reimport>0.51%@+16322, <reimport>0.24%@+16339] dst_divs"
This is due to two issues:
- We have an overlap between the buffer used for copying the input
data (SEC1 doesn't do scatter/gather) and the chained descriptor.
- Data copy is wrong when the previous hash left less than one
blocksize of data to hash, implying a complement of the previous
block with a few bytes from the new request.
Fix it by:
- Moving the second descriptor after the buffer, as moving the buffer
after the descriptor would make it more complex for other cipher
operations (AEAD, ABLKCIPHER)
- Skip the bytes taken from the new request to complete the previous
one by moving the SG list forward.
Fixes: 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash on SEC1")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-06-24 07:20:16 +00:00
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2010-05-19 19:20:36 +10:00
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crypto: talitos - fix hash on SEC1.
On SEC1, hash provides wrong result when performing hashing in several
steps with input data SG list has more than one element. This was
detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[ 44.185947] alg: hash: md5-talitos test failed (wrong result) on test vector 6, cfg="random: may_sleep use_finup src_divs=[<reimport>25.88%@+8063, <flush>24.19%@+9588, 28.63%@+16333, <reimport>4.60%@+6756, 16.70%@+16281] dst_divs=[71.61%@alignmask+16361, 14.36%@+7756, 14.3%@+"
[ 44.325122] alg: hash: sha1-talitos test failed (wrong result) on test vector 3, cfg="random: inplace use_final src_divs=[<flush,nosimd>16.56%@+16378, <reimport>52.0%@+16329, 21.42%@alignmask+16380, 10.2%@alignmask+16380] iv_offset=39"
[ 44.493500] alg: hash: sha224-talitos test failed (wrong result) on test vector 4, cfg="random: use_final nosimd src_divs=[<reimport>52.27%@+7401, <reimport>17.34%@+16285, <flush>17.71%@+26, 12.68%@+10644] iv_offset=43"
[ 44.673262] alg: hash: sha256-talitos test failed (wrong result) on test vector 4, cfg="random: may_sleep use_finup src_divs=[<reimport>60.6%@+12790, 17.86%@+1329, <reimport>12.64%@alignmask+16300, 8.29%@+15, 0.40%@+13506, <reimport>0.51%@+16322, <reimport>0.24%@+16339] dst_divs"
This is due to two issues:
- We have an overlap between the buffer used for copying the input
data (SEC1 doesn't do scatter/gather) and the chained descriptor.
- Data copy is wrong when the previous hash left less than one
blocksize of data to hash, implying a complement of the previous
block with a few bytes from the new request.
Fix it by:
- Moving the second descriptor after the buffer, as moving the buffer
after the descriptor would make it more complex for other cipher
operations (AEAD, ABLKCIPHER)
- Skip the bytes taken from the new request to complete the previous
one by moving the SG list forward.
Fixes: 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash on SEC1")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-06-24 07:20:16 +00:00
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2019-09-10 06:04:14 +00:00
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2018-02-26 17:40:04 +01:00
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crypto: talitos - fix hash on SEC1.
On SEC1, hash provides wrong result when performing hashing in several
steps with input data SG list has more than one element. This was
detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[ 44.185947] alg: hash: md5-talitos test failed (wrong result) on test vector 6, cfg="random: may_sleep use_finup src_divs=[<reimport>25.88%@+8063, <flush>24.19%@+9588, 28.63%@+16333, <reimport>4.60%@+6756, 16.70%@+16281] dst_divs=[71.61%@alignmask+16361, 14.36%@+7756, 14.3%@+"
[ 44.325122] alg: hash: sha1-talitos test failed (wrong result) on test vector 3, cfg="random: inplace use_final src_divs=[<flush,nosimd>16.56%@+16378, <reimport>52.0%@+16329, 21.42%@alignmask+16380, 10.2%@alignmask+16380] iv_offset=39"
[ 44.493500] alg: hash: sha224-talitos test failed (wrong result) on test vector 4, cfg="random: use_final nosimd src_divs=[<reimport>52.27%@+7401, <reimport>17.34%@+16285, <flush>17.71%@+26, 12.68%@+10644] iv_offset=43"
[ 44.673262] alg: hash: sha256-talitos test failed (wrong result) on test vector 4, cfg="random: may_sleep use_finup src_divs=[<reimport>60.6%@+12790, 17.86%@+1329, <reimport>12.64%@alignmask+16300, 8.29%@+15, 0.40%@+13506, <reimport>0.51%@+16322, <reimport>0.24%@+16339] dst_divs"
This is due to two issues:
- We have an overlap between the buffer used for copying the input
data (SEC1 doesn't do scatter/gather) and the chained descriptor.
- Data copy is wrong when the previous hash left less than one
blocksize of data to hash, implying a complement of the previous
block with a few bytes from the new request.
Fix it by:
- Moving the second descriptor after the buffer, as moving the buffer
after the descriptor would make it more complex for other cipher
operations (AEAD, ABLKCIPHER)
- Skip the bytes taken from the new request to complete the previous
one by moving the SG list forward.
Fixes: 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash on SEC1")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-06-24 07:20:16 +00:00
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2018-02-26 17:40:04 +01:00
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2022-05-08 13:22:50 +08:00
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2018-02-26 17:40:04 +01:00
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2026-03-30 12:28:19 +02:00
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2019-09-10 06:04:14 +00:00
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2010-05-19 19:20:36 +10:00
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crypto: talitos - fix hash on SEC1.
On SEC1, hash provides wrong result when performing hashing in several
steps with input data SG list has more than one element. This was
detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[ 44.185947] alg: hash: md5-talitos test failed (wrong result) on test vector 6, cfg="random: may_sleep use_finup src_divs=[<reimport>25.88%@+8063, <flush>24.19%@+9588, 28.63%@+16333, <reimport>4.60%@+6756, 16.70%@+16281] dst_divs=[71.61%@alignmask+16361, 14.36%@+7756, 14.3%@+"
[ 44.325122] alg: hash: sha1-talitos test failed (wrong result) on test vector 3, cfg="random: inplace use_final src_divs=[<flush,nosimd>16.56%@+16378, <reimport>52.0%@+16329, 21.42%@alignmask+16380, 10.2%@alignmask+16380] iv_offset=39"
[ 44.493500] alg: hash: sha224-talitos test failed (wrong result) on test vector 4, cfg="random: use_final nosimd src_divs=[<reimport>52.27%@+7401, <reimport>17.34%@+16285, <flush>17.71%@+26, 12.68%@+10644] iv_offset=43"
[ 44.673262] alg: hash: sha256-talitos test failed (wrong result) on test vector 4, cfg="random: may_sleep use_finup src_divs=[<reimport>60.6%@+12790, 17.86%@+1329, <reimport>12.64%@alignmask+16300, 8.29%@+15, 0.40%@+13506, <reimport>0.51%@+16322, <reimport>0.24%@+16339] dst_divs"
This is due to two issues:
- We have an overlap between the buffer used for copying the input
data (SEC1 doesn't do scatter/gather) and the chained descriptor.
- Data copy is wrong when the previous hash left less than one
blocksize of data to hash, implying a complement of the previous
block with a few bytes from the new request.
Fix it by:
- Moving the second descriptor after the buffer, as moving the buffer
after the descriptor would make it more complex for other cipher
operations (AEAD, ABLKCIPHER)
- Skip the bytes taken from the new request to complete the previous
one by moving the SG list forward.
Fixes: 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash on SEC1")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-06-24 07:20:16 +00:00
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2015-04-17 16:31:51 +02:00
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2018-02-26 17:40:04 +01:00
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2022-05-08 13:22:50 +08:00
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2018-02-26 17:40:04 +01:00
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2010-05-19 19:20:36 +10:00
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2022-05-08 13:22:50 +08:00
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2017-10-06 15:05:06 +02:00
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2010-05-19 19:20:36 +10:00
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2026-03-30 12:28:19 +02:00
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2010-05-19 19:20:36 +10:00
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2017-10-06 15:05:08 +02:00
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2010-06-16 15:29:15 +10:00
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2010-05-19 19:20:36 +10:00
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2026-03-30 12:28:18 +02:00
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2010-05-19 19:20:36 +10:00
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2015-04-17 16:32:18 +02:00
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2017-10-06 15:04:47 +02:00
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2015-04-17 16:32:18 +02:00
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2010-05-19 19:20:36 +10:00
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2015-04-17 16:31:51 +02:00
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2016-06-06 13:20:38 +02:00
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2015-04-17 16:32:07 +02:00
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2016-06-06 13:20:38 +02:00
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2010-05-19 19:20:36 +10:00
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2010-05-19 19:21:53 +10:00
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2026-03-30 12:28:19 +02:00
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2018-02-26 17:40:06 +01:00
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2010-05-19 19:21:53 +10:00
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2010-05-19 19:20:36 +10:00
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2017-09-13 12:44:51 +02:00
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2026-03-30 12:28:19 +02:00
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2010-05-19 19:20:36 +10:00
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2017-10-06 15:05:02 +02:00
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2010-05-19 19:20:36 +10:00
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2017-10-06 15:05:06 +02:00
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2016-06-06 13:20:38 +02:00
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crypto: talitos - fix hash on SEC1.
On SEC1, hash provides wrong result when performing hashing in several
steps with input data SG list has more than one element. This was
detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[ 44.185947] alg: hash: md5-talitos test failed (wrong result) on test vector 6, cfg="random: may_sleep use_finup src_divs=[<reimport>25.88%@+8063, <flush>24.19%@+9588, 28.63%@+16333, <reimport>4.60%@+6756, 16.70%@+16281] dst_divs=[71.61%@alignmask+16361, 14.36%@+7756, 14.3%@+"
[ 44.325122] alg: hash: sha1-talitos test failed (wrong result) on test vector 3, cfg="random: inplace use_final src_divs=[<flush,nosimd>16.56%@+16378, <reimport>52.0%@+16329, 21.42%@alignmask+16380, 10.2%@alignmask+16380] iv_offset=39"
[ 44.493500] alg: hash: sha224-talitos test failed (wrong result) on test vector 4, cfg="random: use_final nosimd src_divs=[<reimport>52.27%@+7401, <reimport>17.34%@+16285, <flush>17.71%@+26, 12.68%@+10644] iv_offset=43"
[ 44.673262] alg: hash: sha256-talitos test failed (wrong result) on test vector 4, cfg="random: may_sleep use_finup src_divs=[<reimport>60.6%@+12790, 17.86%@+1329, <reimport>12.64%@alignmask+16300, 8.29%@+15, 0.40%@+13506, <reimport>0.51%@+16322, <reimport>0.24%@+16339] dst_divs"
This is due to two issues:
- We have an overlap between the buffer used for copying the input
data (SEC1 doesn't do scatter/gather) and the chained descriptor.
- Data copy is wrong when the previous hash left less than one
blocksize of data to hash, implying a complement of the previous
block with a few bytes from the new request.
Fix it by:
- Moving the second descriptor after the buffer, as moving the buffer
after the descriptor would make it more complex for other cipher
operations (AEAD, ABLKCIPHER)
- Skip the bytes taken from the new request to complete the previous
one by moving the SG list forward.
Fixes: 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash on SEC1")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-06-24 07:20:16 +00:00
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|
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|
2017-10-06 15:05:06 +02:00
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|
|
2016-06-06 13:20:38 +02:00
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2010-05-19 19:20:36 +10:00
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2017-10-06 15:05:06 +02:00
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2018-02-26 17:40:04 +01:00
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2017-10-06 15:05:06 +02:00
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|
|
crypto: talitos - fix hash on SEC1.
On SEC1, hash provides wrong result when performing hashing in several
steps with input data SG list has more than one element. This was
detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[ 44.185947] alg: hash: md5-talitos test failed (wrong result) on test vector 6, cfg="random: may_sleep use_finup src_divs=[<reimport>25.88%@+8063, <flush>24.19%@+9588, 28.63%@+16333, <reimport>4.60%@+6756, 16.70%@+16281] dst_divs=[71.61%@alignmask+16361, 14.36%@+7756, 14.3%@+"
[ 44.325122] alg: hash: sha1-talitos test failed (wrong result) on test vector 3, cfg="random: inplace use_final src_divs=[<flush,nosimd>16.56%@+16378, <reimport>52.0%@+16329, 21.42%@alignmask+16380, 10.2%@alignmask+16380] iv_offset=39"
[ 44.493500] alg: hash: sha224-talitos test failed (wrong result) on test vector 4, cfg="random: use_final nosimd src_divs=[<reimport>52.27%@+7401, <reimport>17.34%@+16285, <flush>17.71%@+26, 12.68%@+10644] iv_offset=43"
[ 44.673262] alg: hash: sha256-talitos test failed (wrong result) on test vector 4, cfg="random: may_sleep use_finup src_divs=[<reimport>60.6%@+12790, 17.86%@+1329, <reimport>12.64%@alignmask+16300, 8.29%@+15, 0.40%@+13506, <reimport>0.51%@+16322, <reimport>0.24%@+16339] dst_divs"
This is due to two issues:
- We have an overlap between the buffer used for copying the input
data (SEC1 doesn't do scatter/gather) and the chained descriptor.
- Data copy is wrong when the previous hash left less than one
blocksize of data to hash, implying a complement of the previous
block with a few bytes from the new request.
Fix it by:
- Moving the second descriptor after the buffer, as moving the buffer
after the descriptor would make it more complex for other cipher
operations (AEAD, ABLKCIPHER)
- Skip the bytes taken from the new request to complete the previous
one by moving the SG list forward.
Fixes: 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash on SEC1")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-06-24 07:20:16 +00:00
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2017-10-06 15:05:06 +02:00
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2010-05-19 19:20:36 +10:00
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2026-03-30 12:28:19 +02:00
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|
2010-05-19 19:20:36 +10:00
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2019-09-10 06:04:14 +00:00
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2010-05-19 19:20:36 +10:00
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2018-02-26 17:40:06 +01:00
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2010-05-19 19:20:36 +10:00
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2015-04-17 16:32:18 +02:00
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2017-10-06 15:05:06 +02:00
|
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|
|
crypto: talitos - fix hash on SEC1.
On SEC1, hash provides wrong result when performing hashing in several
steps with input data SG list has more than one element. This was
detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[ 44.185947] alg: hash: md5-talitos test failed (wrong result) on test vector 6, cfg="random: may_sleep use_finup src_divs=[<reimport>25.88%@+8063, <flush>24.19%@+9588, 28.63%@+16333, <reimport>4.60%@+6756, 16.70%@+16281] dst_divs=[71.61%@alignmask+16361, 14.36%@+7756, 14.3%@+"
[ 44.325122] alg: hash: sha1-talitos test failed (wrong result) on test vector 3, cfg="random: inplace use_final src_divs=[<flush,nosimd>16.56%@+16378, <reimport>52.0%@+16329, 21.42%@alignmask+16380, 10.2%@alignmask+16380] iv_offset=39"
[ 44.493500] alg: hash: sha224-talitos test failed (wrong result) on test vector 4, cfg="random: use_final nosimd src_divs=[<reimport>52.27%@+7401, <reimport>17.34%@+16285, <flush>17.71%@+26, 12.68%@+10644] iv_offset=43"
[ 44.673262] alg: hash: sha256-talitos test failed (wrong result) on test vector 4, cfg="random: may_sleep use_finup src_divs=[<reimport>60.6%@+12790, 17.86%@+1329, <reimport>12.64%@alignmask+16300, 8.29%@+15, 0.40%@+13506, <reimport>0.51%@+16322, <reimport>0.24%@+16339] dst_divs"
This is due to two issues:
- We have an overlap between the buffer used for copying the input
data (SEC1 doesn't do scatter/gather) and the chained descriptor.
- Data copy is wrong when the previous hash left less than one
blocksize of data to hash, implying a complement of the previous
block with a few bytes from the new request.
Fix it by:
- Moving the second descriptor after the buffer, as moving the buffer
after the descriptor would make it more complex for other cipher
operations (AEAD, ABLKCIPHER)
- Skip the bytes taken from the new request to complete the previous
one by moving the SG list forward.
Fixes: 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash on SEC1")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-06-24 07:20:16 +00:00
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2017-10-06 15:05:06 +02:00
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2018-02-26 17:40:04 +01:00
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2018-02-26 17:40:06 +01:00
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2017-10-06 15:05:06 +02:00
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|
|
|
crypto: talitos - fix hash on SEC1.
On SEC1, hash provides wrong result when performing hashing in several
steps with input data SG list has more than one element. This was
detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[ 44.185947] alg: hash: md5-talitos test failed (wrong result) on test vector 6, cfg="random: may_sleep use_finup src_divs=[<reimport>25.88%@+8063, <flush>24.19%@+9588, 28.63%@+16333, <reimport>4.60%@+6756, 16.70%@+16281] dst_divs=[71.61%@alignmask+16361, 14.36%@+7756, 14.3%@+"
[ 44.325122] alg: hash: sha1-talitos test failed (wrong result) on test vector 3, cfg="random: inplace use_final src_divs=[<flush,nosimd>16.56%@+16378, <reimport>52.0%@+16329, 21.42%@alignmask+16380, 10.2%@alignmask+16380] iv_offset=39"
[ 44.493500] alg: hash: sha224-talitos test failed (wrong result) on test vector 4, cfg="random: use_final nosimd src_divs=[<reimport>52.27%@+7401, <reimport>17.34%@+16285, <flush>17.71%@+26, 12.68%@+10644] iv_offset=43"
[ 44.673262] alg: hash: sha256-talitos test failed (wrong result) on test vector 4, cfg="random: may_sleep use_finup src_divs=[<reimport>60.6%@+12790, 17.86%@+1329, <reimport>12.64%@alignmask+16300, 8.29%@+15, 0.40%@+13506, <reimport>0.51%@+16322, <reimport>0.24%@+16339] dst_divs"
This is due to two issues:
- We have an overlap between the buffer used for copying the input
data (SEC1 doesn't do scatter/gather) and the chained descriptor.
- Data copy is wrong when the previous hash left less than one
blocksize of data to hash, implying a complement of the previous
block with a few bytes from the new request.
Fix it by:
- Moving the second descriptor after the buffer, as moving the buffer
after the descriptor would make it more complex for other cipher
operations (AEAD, ABLKCIPHER)
- Skip the bytes taken from the new request to complete the previous
one by moving the SG list forward.
Fixes: 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash on SEC1")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-06-24 07:20:16 +00:00
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2017-10-06 15:05:06 +02:00
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2026-03-30 12:28:19 +02:00
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2018-02-26 17:40:06 +01:00
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2017-10-06 15:05:06 +02:00
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2016-06-06 13:20:38 +02:00
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2011-07-15 11:21:38 +08:00
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2010-05-19 19:20:36 +10:00
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2017-10-06 15:05:06 +02:00
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2010-05-19 19:20:36 +10:00
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2015-07-30 17:53:22 +08:00
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2013-11-28 15:11:17 +02:00
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2010-05-19 19:20:36 +10:00
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2026-03-30 12:28:18 +02:00
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2026-03-30 12:28:19 +02:00
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2026-03-30 12:28:18 +02:00
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2026-03-30 12:28:19 +02:00
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2026-03-30 12:28:18 +02:00
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2026-03-30 12:28:19 +02:00
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2026-03-30 12:28:18 +02:00
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2026-03-30 12:28:19 +02:00
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2026-03-30 12:28:18 +02:00
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2026-03-30 12:28:19 +02:00
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2026-03-30 12:28:18 +02:00
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2026-03-30 12:28:19 +02:00
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2026-03-30 12:28:18 +02:00
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2026-03-30 12:28:19 +02:00
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2026-03-30 12:28:18 +02:00
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2010-05-19 19:20:36 +10:00
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2018-02-26 17:40:06 +01:00
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2010-05-19 19:20:36 +10:00
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2017-10-06 15:05:04 +02:00
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2018-02-26 17:40:06 +01:00
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2010-05-19 19:20:36 +10:00
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2017-10-06 15:05:08 +02:00
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2010-06-16 15:29:15 +10:00
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2026-03-30 12:28:19 +02:00
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2010-05-19 19:21:53 +10:00
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2017-10-06 15:05:04 +02:00
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2010-05-19 19:20:36 +10:00
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2017-10-06 15:05:04 +02:00
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2026-03-30 12:28:18 +02:00
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2026-03-30 12:28:19 +02:00
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2026-03-30 12:28:18 +02:00
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2010-05-19 19:20:36 +10:00
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2018-02-26 17:40:06 +01:00
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2010-05-19 19:20:36 +10:00
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2010-05-19 19:21:53 +10:00
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2010-09-23 15:56:38 +08:00
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2010-05-19 19:21:53 +10:00
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2018-02-26 17:40:06 +01:00
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2010-05-19 19:21:53 +10:00
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2010-05-19 19:20:36 +10:00
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2026-03-30 12:28:18 +02:00
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2010-05-19 19:20:36 +10:00
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2026-03-30 12:28:18 +02:00
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2010-05-19 19:20:36 +10:00
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2026-03-30 12:28:18 +02:00
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2010-05-19 19:20:36 +10:00
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2023-10-22 01:10:57 -07:00
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2010-05-19 19:20:36 +10:00
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2023-10-22 01:10:57 -07:00
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2010-05-19 19:20:36 +10:00
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2016-04-21 19:24:55 +03:00
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2018-02-26 17:40:06 +01:00
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2016-04-21 19:24:55 +03:00
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2017-10-06 15:05:08 +02:00
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2016-04-21 19:24:55 +03:00
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2026-03-30 12:28:19 +02:00
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2016-04-21 19:24:55 +03:00
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2018-02-26 17:40:06 +01:00
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2016-04-21 19:24:55 +03:00
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2017-10-06 15:05:04 +02:00
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2018-02-26 17:40:06 +01:00
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2016-04-21 19:24:55 +03:00
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2017-10-06 15:05:04 +02:00
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2016-04-21 19:24:55 +03:00
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2017-10-06 15:05:04 +02:00
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2017-10-06 15:05:08 +02:00
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2016-04-21 19:24:55 +03:00
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2026-03-30 12:28:19 +02:00
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2016-04-21 19:24:55 +03:00
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2018-02-26 17:40:06 +01:00
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2016-04-21 19:24:55 +03:00
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2011-11-21 16:13:25 +08:00
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2017-10-18 08:00:49 +01:00
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2011-11-21 16:13:25 +08:00
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2017-10-18 08:00:49 +01:00
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2011-11-21 16:13:25 +08:00
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2017-10-18 08:00:49 +01:00
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2011-11-21 16:13:25 +08:00
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2017-10-18 08:00:49 +01:00
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2011-11-21 16:13:25 +08:00
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2017-10-06 15:05:02 +02:00
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2011-11-21 16:13:25 +08:00
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|
crypto: remove CRYPTO_TFM_RES_BAD_KEY_LEN
The CRYPTO_TFM_RES_BAD_KEY_LEN flag was apparently meant as a way to
make the ->setkey() functions provide more information about errors.
However, no one actually checks for this flag, which makes it pointless.
Also, many algorithms fail to set this flag when given a bad length key.
Reviewing just the generic implementations, this is the case for
aes-fixed-time, cbcmac, echainiv, nhpoly1305, pcrypt, rfc3686, rfc4309,
rfc7539, rfc7539esp, salsa20, seqiv, and xcbc. But there are probably
many more in arch/*/crypto/ and drivers/crypto/.
Some algorithms can even set this flag when the key is the correct
length. For example, authenc and authencesn set it when the key payload
is malformed in any way (not just a bad length), the atmel-sha and ccree
drivers can set it if a memory allocation fails, and the chelsio driver
sets it for bad auth tag lengths, not just bad key lengths.
So even if someone actually wanted to start checking this flag (which
seems unlikely, since it's been unused for a long time), there would be
a lot of work needed to get it working correctly. But it would probably
be much better to go back to the drawing board and just define different
return values, like -EINVAL if the key is invalid for the algorithm vs.
-EKEYREJECTED if the key was rejected by a policy like "no weak keys".
That would be much simpler, less error-prone, and easier to test.
So just remove this flag.
Signed-off-by: Eric Biggers <ebiggers@google.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-12-30 21:19:36 -06:00
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2011-11-21 16:13:25 +08:00
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2017-10-06 15:05:02 +02:00
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2011-11-21 16:13:25 +08:00
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2017-10-06 15:05:02 +02:00
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2011-11-21 16:13:25 +08:00
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2008-06-23 19:50:15 +08:00
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2010-05-19 19:18:38 +10:00
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2016-06-06 13:20:44 +02:00
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2010-05-19 19:18:38 +10:00
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2019-11-09 18:09:49 +01:00
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2010-05-19 19:19:33 +10:00
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2015-07-30 17:53:22 +08:00
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2010-05-19 19:18:38 +10:00
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2008-06-23 19:50:15 +08:00
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Revert "crypto: talitos - add IPsec ESN support"
This reverts commit e763eb699be723fb41af818118068c6b3afdaf8d.
Current IPsec ESN implementation for authencesn(cbc(aes), hmac(sha))
(separate encryption and integrity algorithms) does not conform
to RFC4303.
ICV is generated by hashing the sequence
SPI, SeqNum-High, SeqNum-Low, IV, Payload
instead of
SPI, SeqNum-Low, IV, Payload, SeqNum-High.
Cc: <stable@vger.kernel.org> # 3.8, 3.7
Reported-by: Chaoxing Lin <Chaoxing.Lin@ultra-3eti.com>
Signed-off-by: Horia Geanta <horia.geanta@freescale.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-03-20 16:31:38 +02:00
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2020-07-09 23:20:41 -07:00
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2015-07-30 17:53:22 +08:00
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2009-03-29 15:50:50 +08:00
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2008-06-23 19:50:15 +08:00
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2008-07-03 19:08:46 +08:00
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2016-06-06 13:20:46 +02:00
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2019-05-21 13:34:08 +00:00
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2016-06-06 13:20:46 +02:00
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2020-07-09 23:20:41 -07:00
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2010-05-19 19:18:38 +10:00
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2015-07-30 17:53:22 +08:00
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2020-07-09 23:20:41 -07:00
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2015-07-30 17:53:22 +08:00
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2019-04-11 16:51:21 +08:00
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2009-03-29 15:50:50 +08:00
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2008-07-03 19:08:46 +08:00
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2008-07-10 18:29:18 +08:00
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2016-06-06 13:20:46 +02:00
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2019-05-21 13:34:08 +00:00
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2012-07-03 19:16:53 +03:00
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2015-07-30 17:53:22 +08:00
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2012-07-03 19:16:53 +03:00
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2019-05-21 13:34:08 +00:00
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2016-06-06 13:20:46 +02:00
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2015-07-30 17:53:22 +08:00
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2019-04-11 16:51:21 +08:00
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2010-05-19 19:18:38 +10:00
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2010-05-19 19:18:38 +10:00
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2015-07-30 17:53:22 +08:00
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2020-07-09 23:20:41 -07:00
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2015-07-30 17:53:22 +08:00
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2019-04-11 16:51:21 +08:00
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2009-03-29 15:50:50 +08:00
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2008-07-10 18:29:18 +08:00
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2009-03-29 15:52:32 +08:00
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2016-06-06 13:20:46 +02:00
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2019-05-21 13:34:08 +00:00
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2016-06-06 13:20:46 +02:00
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2020-07-09 23:20:41 -07:00
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2016-06-06 13:20:46 +02:00
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2019-04-11 16:51:21 +08:00
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2016-06-06 13:20:46 +02:00
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2019-11-09 18:09:49 +01:00
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2020-07-09 23:20:41 -07:00
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2019-11-09 18:09:49 +01:00
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2015-12-01 12:44:15 +01:00
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2019-11-09 18:09:49 +01:00
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2020-07-09 23:20:41 -07:00
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2019-11-09 18:09:49 +01:00
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2009-03-29 15:52:32 +08:00
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2019-11-09 18:09:49 +01:00
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2020-07-09 23:20:41 -07:00
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2019-11-09 18:09:49 +01:00
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2015-12-01 12:44:15 +01:00
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2017-10-06 15:04:43 +02:00
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2015-12-01 12:44:15 +01:00
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2021-01-20 18:57:25 +00:00
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2019-11-09 18:09:49 +01:00
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2020-07-09 23:20:41 -07:00
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2019-11-09 18:09:49 +01:00
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2015-12-01 12:44:15 +01:00
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2019-11-09 18:09:49 +01:00
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2020-07-09 23:20:41 -07:00
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2019-11-09 18:09:49 +01:00
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2015-12-01 12:44:15 +01:00
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2019-11-09 18:09:49 +01:00
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2020-07-09 23:20:41 -07:00
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2019-11-09 18:09:49 +01:00
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2015-12-01 12:44:15 +01:00
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2019-11-09 18:09:49 +01:00
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2020-07-09 23:20:41 -07:00
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2019-11-09 18:09:49 +01:00
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2009-03-29 15:52:32 +08:00
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2010-05-19 19:20:36 +10:00
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2016-04-21 19:24:55 +03:00
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2010-05-19 19:20:36 +10:00
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2015-03-03 08:21:34 -05:00
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2020-07-09 23:20:41 -07:00
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2010-05-19 19:20:36 +10:00
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2016-04-21 19:24:55 +03:00
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2010-05-19 19:20:36 +10:00
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2020-07-09 23:20:41 -07:00
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2010-05-19 19:20:36 +10:00
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2010-05-19 19:21:53 +10:00
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2016-04-21 19:24:55 +03:00
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2010-05-19 19:21:53 +10:00
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2020-07-09 23:20:41 -07:00
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2010-05-19 19:21:53 +10:00
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2010-05-19 19:20:36 +10:00
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2016-04-21 19:24:55 +03:00
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2010-05-19 19:20:36 +10:00
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2020-07-09 23:20:41 -07:00
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2010-05-19 19:20:36 +10:00
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2016-04-21 19:24:55 +03:00
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2010-05-19 19:20:36 +10:00
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2020-07-09 23:20:41 -07:00
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2010-05-19 19:20:36 +10:00
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2016-04-21 19:24:55 +03:00
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2010-05-19 19:20:36 +10:00
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2020-07-09 23:20:41 -07:00
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2010-05-19 19:20:36 +10:00
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2011-11-21 16:13:25 +08:00
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2016-04-21 19:24:55 +03:00
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2011-11-21 16:13:25 +08:00
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2015-03-03 08:21:34 -05:00
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2020-07-09 23:20:41 -07:00
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2011-11-21 16:13:25 +08:00
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2016-04-21 19:24:55 +03:00
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2011-11-21 16:13:25 +08:00
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2020-07-09 23:20:41 -07:00
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2011-11-21 16:13:25 +08:00
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2016-04-21 19:24:55 +03:00
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2011-11-21 16:13:25 +08:00
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2020-07-09 23:20:41 -07:00
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2011-11-21 16:13:25 +08:00
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2016-04-21 19:24:55 +03:00
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2011-11-21 16:13:25 +08:00
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2020-07-09 23:20:41 -07:00
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2011-11-21 16:13:25 +08:00
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2016-04-21 19:24:55 +03:00
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2011-11-21 16:13:25 +08:00
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2020-07-09 23:20:41 -07:00
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2011-11-21 16:13:25 +08:00
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2016-04-21 19:24:55 +03:00
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2011-11-21 16:13:25 +08:00
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2020-07-09 23:20:41 -07:00
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2011-11-21 16:13:25 +08:00
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2008-06-23 19:50:15 +08:00
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2010-05-19 19:19:33 +10:00
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2008-06-23 19:50:15 +08:00
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2016-04-19 20:33:47 +03:00
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2008-06-23 19:50:15 +08:00
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2011-07-15 11:21:38 +08:00
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2008-06-23 19:50:15 +08:00
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2009-03-29 15:53:59 +08:00
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2011-07-15 11:21:38 +08:00
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2008-06-23 19:50:15 +08:00
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2010-05-19 19:19:33 +10:00
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2008-06-23 19:50:15 +08:00
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2011-07-15 11:21:39 +08:00
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2010-05-19 19:20:36 +10:00
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2015-07-30 17:53:22 +08:00
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2010-05-19 19:20:36 +10:00
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2016-04-19 20:33:47 +03:00
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2008-06-23 19:50:15 +08:00
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2019-11-09 18:09:49 +01:00
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2010-05-19 19:20:36 +10:00
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2019-11-09 18:09:49 +01:00
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2010-05-19 19:20:36 +10:00
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2019-11-09 18:09:49 +01:00
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2010-05-19 19:20:36 +10:00
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2019-11-09 18:09:49 +01:00
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2010-05-19 19:20:36 +10:00
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2017-10-06 15:05:02 +02:00
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2008-06-23 19:50:15 +08:00
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2023-10-20 09:56:02 +02:00
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2008-06-23 19:50:15 +08:00
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2010-05-19 19:19:33 +10:00
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2019-11-09 18:09:49 +01:00
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2010-05-19 19:19:33 +10:00
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2015-07-30 17:53:22 +08:00
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2019-09-09 00:29:52 -05:00
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2010-05-19 19:19:33 +10:00
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2008-06-23 19:50:15 +08:00
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2011-11-21 16:13:27 +08:00
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2011-12-12 14:59:11 -06:00
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2011-11-21 16:13:27 +08:00
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2008-06-23 19:50:15 +08:00
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2011-11-21 16:13:27 +08:00
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2011-12-12 14:59:11 -06:00
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2011-11-21 16:13:27 +08:00
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2008-06-23 19:50:15 +08:00
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2010-05-19 19:21:53 +10:00
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2008-06-23 19:50:15 +08:00
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2017-10-06 15:04:49 +02:00
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2008-06-23 19:50:15 +08:00
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2010-05-19 19:19:33 +10:00
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2019-11-09 18:09:49 +01:00
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2017-10-06 15:05:02 +02:00
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2019-11-09 18:09:49 +01:00
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2021-01-20 18:57:25 +00:00
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2010-05-19 19:20:36 +10:00
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2010-05-19 19:19:33 +10:00
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2015-07-30 17:53:22 +08:00
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2017-10-06 15:05:02 +02:00
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2015-07-30 17:53:22 +08:00
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2019-04-11 16:51:21 +08:00
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2015-07-30 17:53:22 +08:00
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2017-10-06 15:04:39 +02:00
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2017-10-06 15:04:49 +02:00
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2017-10-06 15:04:39 +02:00
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2010-05-19 19:19:33 +10:00
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2010-05-19 19:20:36 +10:00
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2018-02-26 17:40:04 +01:00
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2012-08-08 20:33:34 -05:00
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crypto: talitos - Don't provide setkey for non hmac hashing algs.
Today, md5sum fails with error -ENOKEY because a setkey
function is set for non hmac hashing algs, see strace output below:
mmap(NULL, 378880, PROT_READ, MAP_SHARED, 6, 0) = 0x77f50000
accept(3, 0, NULL) = 7
vmsplice(5, [{"bin/\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"..., 378880}], 1, SPLICE_F_MORE|SPLICE_F_GIFT) = 262144
splice(4, NULL, 7, NULL, 262144, SPLICE_F_MORE) = -1 ENOKEY (Required key not available)
write(2, "Generation of hash for file kcap"..., 50) = 50
munmap(0x77f50000, 378880) = 0
This patch ensures that setkey() function is set only
for hmac hashing.
Cc: <stable@vger.kernel.org>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-12 11:03:39 +02:00
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2016-04-21 19:24:55 +03:00
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2012-08-08 20:33:34 -05:00
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2011-11-21 16:13:25 +08:00
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2011-12-12 14:59:10 -06:00
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2017-10-06 15:04:49 +02:00
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2011-11-21 16:13:25 +08:00
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2011-12-12 14:59:10 -06:00
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2010-05-19 19:21:53 +10:00
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2011-11-21 16:13:25 +08:00
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2010-05-19 19:21:53 +10:00
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2023-10-22 01:10:57 -07:00
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2010-05-19 19:21:53 +10:00
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2010-05-19 19:20:36 +10:00
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2010-09-23 15:55:27 +08:00
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2017-10-06 15:04:49 +02:00
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2010-09-23 15:55:27 +08:00
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2010-05-19 19:19:33 +10:00
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2008-06-23 19:50:15 +08:00
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2016-06-06 13:20:44 +02:00
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2023-10-22 01:10:39 -07:00
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2019-05-21 13:34:18 +00:00
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2008-06-23 19:50:15 +08:00
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2011-11-01 13:39:56 +01:00
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2008-06-23 19:50:15 +08:00
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2011-11-21 16:13:27 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2011-11-21 16:13:27 +08:00
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2011-12-12 14:59:11 -06:00
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2011-11-21 16:13:27 +08:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2011-11-21 16:13:27 +08:00
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2011-12-12 14:59:11 -06:00
|
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|
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
|
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2011-11-21 16:13:27 +08:00
|
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|
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
|
|
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|
2011-11-21 16:13:27 +08:00
|
|
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|
|
|
|
|
|
|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
|
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|
2011-11-21 16:13:27 +08:00
|
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2011-12-12 14:59:11 -06:00
|
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|
2011-11-21 16:13:27 +08:00
|
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2011-12-12 14:59:11 -06:00
|
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2011-11-21 16:13:27 +08:00
|
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2011-02-17 02:43:24 -07:00
|
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2008-06-23 19:50:15 +08:00
|
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2010-04-13 16:12:29 -07:00
|
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2008-06-23 19:50:15 +08:00
|
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|
2015-04-17 16:32:11 +02:00
|
|
|
|
2017-10-06 15:04:53 +02:00
|
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|
|
2008-06-23 19:50:15 +08:00
|
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|
|
2017-10-06 15:04:49 +02:00
|
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|
|
2008-06-23 19:50:15 +08:00
|
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2014-01-28 20:17:23 +08:00
|
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2008-06-23 19:50:15 +08:00
|
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2012-03-30 17:49:53 +03:00
|
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2017-10-06 15:04:53 +02:00
|
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2008-06-23 19:50:15 +08:00
|
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2017-10-06 15:04:51 +02:00
|
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2008-06-23 19:50:15 +08:00
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2008-07-30 16:26:57 +08:00
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2008-10-12 20:33:14 +08:00
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2010-05-19 19:21:53 +10:00
|
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2011-11-21 16:13:25 +08:00
|
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2008-10-12 20:33:14 +08:00
|
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|
|
2015-04-17 16:32:05 +02:00
|
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2015-04-17 16:32:11 +02:00
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|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2019-06-17 21:14:45 +00:00
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2017-10-06 15:04:55 +02:00
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crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
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2017-10-06 15:04:55 +02:00
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|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
|
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2017-10-06 15:04:55 +02:00
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|
crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-04-17 16:32:13 +02:00
|
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treewide: devm_kzalloc() -> devm_kcalloc()
The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc().
This patch replaces cases of:
devm_kzalloc(handle, a * b, gfp)
with:
devm_kcalloc(handle, a * b, gfp)
as well as handling cases of:
devm_kzalloc(handle, a * b * c, gfp)
with:
devm_kzalloc(handle, array3_size(a, b, c), gfp)
as it's slightly less ugly than:
devm_kcalloc(handle, array_size(a, b), c, gfp)
This does, however, attempt to ignore constant size factors like:
devm_kzalloc(handle, 4 * 1024, gfp)
though any constants defined via macros get caught up in the conversion.
Any factors with a sizeof() of "unsigned char", "char", and "u8" were
dropped, since they're redundant.
Some manual whitespace fixes were needed in this patch, as Coccinelle
really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...".
The Coccinelle script used for this was:
// Fix redundant parens around sizeof().
@@
expression HANDLE;
type TYPE;
expression THING, E;
@@
(
devm_kzalloc(HANDLE,
- (sizeof(TYPE)) * E
+ sizeof(TYPE) * E
, ...)
|
devm_kzalloc(HANDLE,
- (sizeof(THING)) * E
+ sizeof(THING) * E
, ...)
)
// Drop single-byte sizes and redundant parens.
@@
expression HANDLE;
expression COUNT;
typedef u8;
typedef __u8;
@@
(
devm_kzalloc(HANDLE,
- sizeof(u8) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(__u8) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(char) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(unsigned char) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(u8) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(__u8) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(char) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(unsigned char) * COUNT
+ COUNT
, ...)
)
// 2-factor product with sizeof(type/expression) and identifier or constant.
@@
expression HANDLE;
type TYPE;
expression THING;
identifier COUNT_ID;
constant COUNT_CONST;
@@
(
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (COUNT_ID)
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * COUNT_ID
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (COUNT_CONST)
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * COUNT_CONST
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (COUNT_ID)
+ COUNT_ID, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * COUNT_ID
+ COUNT_ID, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (COUNT_CONST)
+ COUNT_CONST, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * COUNT_CONST
+ COUNT_CONST, sizeof(THING)
, ...)
)
// 2-factor product, only identifiers.
@@
expression HANDLE;
identifier SIZE, COUNT;
@@
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- SIZE * COUNT
+ COUNT, SIZE
, ...)
// 3-factor product with 1 sizeof(type) or sizeof(expression), with
// redundant parens removed.
@@
expression HANDLE;
expression THING;
identifier STRIDE, COUNT;
type TYPE;
@@
(
devm_kzalloc(HANDLE,
- sizeof(TYPE) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
)
// 3-factor product with 2 sizeof(variable), with redundant parens removed.
@@
expression HANDLE;
expression THING1, THING2;
identifier COUNT;
type TYPE1, TYPE2;
@@
(
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(TYPE2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
)
// 3-factor product, only identifiers, with redundant parens removed.
@@
expression HANDLE;
identifier STRIDE, SIZE, COUNT;
@@
(
devm_kzalloc(HANDLE,
- (COUNT) * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
)
// Any remaining multi-factor products, first at least 3-factor products,
// when they're not all constants...
@@
expression HANDLE;
expression E1, E2, E3;
constant C1, C2, C3;
@@
(
devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
devm_kzalloc(HANDLE,
- (E1) * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- (E1) * (E2) * E3
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- (E1) * (E2) * (E3)
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- E1 * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
)
// And then all remaining 2 factors products when they're not all constants,
// keeping sizeof() as the second factor argument.
@@
expression HANDLE;
expression THING, E1, E2;
type TYPE;
constant C1, C2, C3;
@@
(
devm_kzalloc(HANDLE, sizeof(THING) * C2, ...)
|
devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...)
|
devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
devm_kzalloc(HANDLE, C1 * C2, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (E2)
+ E2, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * E2
+ E2, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (E2)
+ E2, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * E2
+ E2, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- (E1) * E2
+ E1, E2
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- (E1) * (E2)
+ E1, E2
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- E1 * E2
+ E1, E2
, ...)
)
Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-12 14:07:58 -07:00
|
|
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|
|
2009-08-13 11:50:38 +10:00
|
|
|
|
|
|
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|
|
2008-06-23 19:50:15 +08:00
|
|
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|
2015-03-03 08:21:33 -05:00
|
|
|
|
|
|
|
|
|
2011-11-21 16:13:27 +08:00
|
|
|
|
2015-04-17 16:32:11 +02:00
|
|
|
|
2011-12-12 14:59:11 -06:00
|
|
|
|
2011-11-21 16:13:27 +08:00
|
|
|
|
2011-11-21 16:13:27 +08:00
|
|
|
|
2009-08-13 11:50:38 +10:00
|
|
|
|
|
|
|
|
|
2008-06-23 19:50:15 +08:00
|
|
|
|
treewide: devm_kzalloc() -> devm_kcalloc()
The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc().
This patch replaces cases of:
devm_kzalloc(handle, a * b, gfp)
with:
devm_kcalloc(handle, a * b, gfp)
as well as handling cases of:
devm_kzalloc(handle, a * b * c, gfp)
with:
devm_kzalloc(handle, array3_size(a, b, c), gfp)
as it's slightly less ugly than:
devm_kcalloc(handle, array_size(a, b), c, gfp)
This does, however, attempt to ignore constant size factors like:
devm_kzalloc(handle, 4 * 1024, gfp)
though any constants defined via macros get caught up in the conversion.
Any factors with a sizeof() of "unsigned char", "char", and "u8" were
dropped, since they're redundant.
Some manual whitespace fixes were needed in this patch, as Coccinelle
really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...".
The Coccinelle script used for this was:
// Fix redundant parens around sizeof().
@@
expression HANDLE;
type TYPE;
expression THING, E;
@@
(
devm_kzalloc(HANDLE,
- (sizeof(TYPE)) * E
+ sizeof(TYPE) * E
, ...)
|
devm_kzalloc(HANDLE,
- (sizeof(THING)) * E
+ sizeof(THING) * E
, ...)
)
// Drop single-byte sizes and redundant parens.
@@
expression HANDLE;
expression COUNT;
typedef u8;
typedef __u8;
@@
(
devm_kzalloc(HANDLE,
- sizeof(u8) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(__u8) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(char) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(unsigned char) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(u8) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(__u8) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(char) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(unsigned char) * COUNT
+ COUNT
, ...)
)
// 2-factor product with sizeof(type/expression) and identifier or constant.
@@
expression HANDLE;
type TYPE;
expression THING;
identifier COUNT_ID;
constant COUNT_CONST;
@@
(
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (COUNT_ID)
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * COUNT_ID
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (COUNT_CONST)
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * COUNT_CONST
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (COUNT_ID)
+ COUNT_ID, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * COUNT_ID
+ COUNT_ID, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (COUNT_CONST)
+ COUNT_CONST, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * COUNT_CONST
+ COUNT_CONST, sizeof(THING)
, ...)
)
// 2-factor product, only identifiers.
@@
expression HANDLE;
identifier SIZE, COUNT;
@@
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- SIZE * COUNT
+ COUNT, SIZE
, ...)
// 3-factor product with 1 sizeof(type) or sizeof(expression), with
// redundant parens removed.
@@
expression HANDLE;
expression THING;
identifier STRIDE, COUNT;
type TYPE;
@@
(
devm_kzalloc(HANDLE,
- sizeof(TYPE) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
)
// 3-factor product with 2 sizeof(variable), with redundant parens removed.
@@
expression HANDLE;
expression THING1, THING2;
identifier COUNT;
type TYPE1, TYPE2;
@@
(
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(TYPE2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
)
// 3-factor product, only identifiers, with redundant parens removed.
@@
expression HANDLE;
identifier STRIDE, SIZE, COUNT;
@@
(
devm_kzalloc(HANDLE,
- (COUNT) * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
)
// Any remaining multi-factor products, first at least 3-factor products,
// when they're not all constants...
@@
expression HANDLE;
expression E1, E2, E3;
constant C1, C2, C3;
@@
(
devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
devm_kzalloc(HANDLE,
- (E1) * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- (E1) * (E2) * E3
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- (E1) * (E2) * (E3)
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- E1 * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
)
// And then all remaining 2 factors products when they're not all constants,
// keeping sizeof() as the second factor argument.
@@
expression HANDLE;
expression THING, E1, E2;
type TYPE;
constant C1, C2, C3;
@@
(
devm_kzalloc(HANDLE, sizeof(THING) * C2, ...)
|
devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...)
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devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
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devm_kzalloc(HANDLE, C1 * C2, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (E2)
+ E2, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * E2
+ E2, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (E2)
+ E2, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * E2
+ E2, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- (E1) * E2
+ E1, E2
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- (E1) * (E2)
+ E1, E2
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- E1 * E2
+ E1, E2
, ...)
)
Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-12 14:07:58 -07:00
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2009-08-13 11:50:38 +10:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:50:38 +10:00
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2015-03-03 08:21:33 -05:00
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2008-06-23 19:50:15 +08:00
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2009-08-13 11:51:51 +10:00
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2008-06-23 19:50:15 +08:00
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2015-07-30 17:53:22 +08:00
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2008-06-23 19:50:15 +08:00
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2011-12-12 14:59:10 -06:00
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2011-11-21 16:13:25 +08:00
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2008-06-23 19:50:15 +08:00
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2010-05-19 19:19:33 +10:00
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2019-11-09 18:09:49 +01:00
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2010-05-19 19:19:33 +10:00
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2015-07-30 17:53:22 +08:00
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2010-05-19 19:19:33 +10:00
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2015-07-30 17:53:22 +08:00
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2010-05-19 19:19:33 +10:00
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2008-06-23 19:50:15 +08:00
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2015-07-30 17:53:22 +08:00
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2017-10-06 15:04:49 +02:00
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Revert "crypto: talitos - add IPsec ESN support"
This reverts commit e763eb699be723fb41af818118068c6b3afdaf8d.
Current IPsec ESN implementation for authencesn(cbc(aes), hmac(sha))
(separate encryption and integrity algorithms) does not conform
to RFC4303.
ICV is generated by hashing the sequence
SPI, SeqNum-High, SeqNum-Low, IV, Payload
instead of
SPI, SeqNum-Low, IV, Payload, SeqNum-High.
Cc: <stable@vger.kernel.org> # 3.8, 3.7
Reported-by: Chaoxing Lin <Chaoxing.Lin@ultra-3eti.com>
Signed-off-by: Horia Geanta <horia.geanta@freescale.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-03-20 16:31:38 +02:00
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2008-06-23 19:50:15 +08:00
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2011-11-21 16:13:26 +08:00
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2008-06-23 19:50:15 +08:00
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2010-01-17 21:54:01 +11:00
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2015-04-17 16:32:20 +02:00
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2008-06-23 19:50:15 +08:00
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2015-04-17 16:32:20 +02:00
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2008-06-23 19:50:15 +08:00
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2011-02-17 02:43:24 -07:00
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2010-04-13 16:13:02 -07:00
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2008-06-23 19:50:15 +08:00
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2024-10-07 22:58:06 +02:00
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2008-06-23 19:50:15 +08:00
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2011-11-26 21:26:19 +08:00
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2008-06-23 19:50:15 +08:00
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