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linux/drivers/memory/dfl-emif.c

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memory: dfl-emif: add the DFL EMIF private feature driver This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control. The purpose of memory clearing block is to zero out all private memory when FPGA is to be reprogrammed. This gives users a reliable method to prevent potential data leakage. [mdf@kernel.org: Fixed up ABI doc] Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20210107043714.991646-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-06 20:37:14 -08:00
memory: dfl-emif: Update the dfl emif driver support revision 1 The next generation (revision 1) of the DFL EMIF feature device requires support for more than 4 memory banks. It does not support the selective clearing of memory banks. A capability register replaces the previous control register, and contains a bitmask to indicate the presence of each memory bank. This bitmask aligns with the previous control register bitmask that served the same purpose. The control and capability registers are treated like a C Union structure in order to support both the new and old revisions of the EMIF device. Signed-off-by: Debarati Biswas <debaratix.biswas@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220713130355.196115-1-tianfei.zhang@intel.com
2022-07-13 09:03:55 -04:00
memory: dfl-emif: add the DFL EMIF private feature driver This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control. The purpose of memory clearing block is to zero out all private memory when FPGA is to be reprogrammed. This gives users a reliable method to prevent potential data leakage. [mdf@kernel.org: Fixed up ABI doc] Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20210107043714.991646-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-06 20:37:14 -08:00
memory: dfl-emif: Update the dfl emif driver support revision 1 The next generation (revision 1) of the DFL EMIF feature device requires support for more than 4 memory banks. It does not support the selective clearing of memory banks. A capability register replaces the previous control register, and contains a bitmask to indicate the presence of each memory bank. This bitmask aligns with the previous control register bitmask that served the same purpose. The control and capability registers are treated like a C Union structure in order to support both the new and old revisions of the EMIF device. Signed-off-by: Debarati Biswas <debaratix.biswas@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220713130355.196115-1-tianfei.zhang@intel.com
2022-07-13 09:03:55 -04:00
memory: dfl-emif: add the DFL EMIF private feature driver This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control. The purpose of memory clearing block is to zero out all private memory when FPGA is to be reprogrammed. This gives users a reliable method to prevent potential data leakage. [mdf@kernel.org: Fixed up ABI doc] Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20210107043714.991646-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-06 20:37:14 -08:00
memory: dfl-emif: Update the dfl emif driver support revision 1 The next generation (revision 1) of the DFL EMIF feature device requires support for more than 4 memory banks. It does not support the selective clearing of memory banks. A capability register replaces the previous control register, and contains a bitmask to indicate the presence of each memory bank. This bitmask aligns with the previous control register bitmask that served the same purpose. The control and capability registers are treated like a C Union structure in order to support both the new and old revisions of the EMIF device. Signed-off-by: Debarati Biswas <debaratix.biswas@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220713130355.196115-1-tianfei.zhang@intel.com
2022-07-13 09:03:55 -04:00
memory: dfl-emif: add the DFL EMIF private feature driver This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control. The purpose of memory clearing block is to zero out all private memory when FPGA is to be reprogrammed. This gives users a reliable method to prevent potential data leakage. [mdf@kernel.org: Fixed up ABI doc] Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20210107043714.991646-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-06 20:37:14 -08:00
memory: dfl-emif: Update the dfl emif driver support revision 1 The next generation (revision 1) of the DFL EMIF feature device requires support for more than 4 memory banks. It does not support the selective clearing of memory banks. A capability register replaces the previous control register, and contains a bitmask to indicate the presence of each memory bank. This bitmask aligns with the previous control register bitmask that served the same purpose. The control and capability registers are treated like a C Union structure in order to support both the new and old revisions of the EMIF device. Signed-off-by: Debarati Biswas <debaratix.biswas@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220713130355.196115-1-tianfei.zhang@intel.com
2022-07-13 09:03:55 -04:00
memory: dfl-emif: add the DFL EMIF private feature driver This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control. The purpose of memory clearing block is to zero out all private memory when FPGA is to be reprogrammed. This gives users a reliable method to prevent potential data leakage. [mdf@kernel.org: Fixed up ABI doc] Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20210107043714.991646-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-06 20:37:14 -08:00
memory: dfl-emif: Update the dfl emif driver support revision 1 The next generation (revision 1) of the DFL EMIF feature device requires support for more than 4 memory banks. It does not support the selective clearing of memory banks. A capability register replaces the previous control register, and contains a bitmask to indicate the presence of each memory bank. This bitmask aligns with the previous control register bitmask that served the same purpose. The control and capability registers are treated like a C Union structure in order to support both the new and old revisions of the EMIF device. Signed-off-by: Debarati Biswas <debaratix.biswas@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220713130355.196115-1-tianfei.zhang@intel.com
2022-07-13 09:03:55 -04:00
memory: dfl-emif: add the DFL EMIF private feature driver This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control. The purpose of memory clearing block is to zero out all private memory when FPGA is to be reprogrammed. This gives users a reliable method to prevent potential data leakage. [mdf@kernel.org: Fixed up ABI doc] Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20210107043714.991646-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-06 20:37:14 -08:00
memory: dfl-emif: Update the dfl emif driver support revision 1 The next generation (revision 1) of the DFL EMIF feature device requires support for more than 4 memory banks. It does not support the selective clearing of memory banks. A capability register replaces the previous control register, and contains a bitmask to indicate the presence of each memory bank. This bitmask aligns with the previous control register bitmask that served the same purpose. The control and capability registers are treated like a C Union structure in order to support both the new and old revisions of the EMIF device. Signed-off-by: Debarati Biswas <debaratix.biswas@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220713130355.196115-1-tianfei.zhang@intel.com
2022-07-13 09:03:55 -04:00
memory: dfl-emif: add the DFL EMIF private feature driver This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control. The purpose of memory clearing block is to zero out all private memory when FPGA is to be reprogrammed. This gives users a reliable method to prevent potential data leakage. [mdf@kernel.org: Fixed up ABI doc] Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20210107043714.991646-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-06 20:37:14 -08:00
memory: dfl-emif: Update the dfl emif driver support revision 1 The next generation (revision 1) of the DFL EMIF feature device requires support for more than 4 memory banks. It does not support the selective clearing of memory banks. A capability register replaces the previous control register, and contains a bitmask to indicate the presence of each memory bank. This bitmask aligns with the previous control register bitmask that served the same purpose. The control and capability registers are treated like a C Union structure in order to support both the new and old revisions of the EMIF device. Signed-off-by: Debarati Biswas <debaratix.biswas@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220713130355.196115-1-tianfei.zhang@intel.com
2022-07-13 09:03:55 -04:00
memory: dfl-emif: add the DFL EMIF private feature driver This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control. The purpose of memory clearing block is to zero out all private memory when FPGA is to be reprogrammed. This gives users a reliable method to prevent potential data leakage. [mdf@kernel.org: Fixed up ABI doc] Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20210107043714.991646-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-06 20:37:14 -08:00
memory: dfl-emif: Update the dfl emif driver support revision 1 The next generation (revision 1) of the DFL EMIF feature device requires support for more than 4 memory banks. It does not support the selective clearing of memory banks. A capability register replaces the previous control register, and contains a bitmask to indicate the presence of each memory bank. This bitmask aligns with the previous control register bitmask that served the same purpose. The control and capability registers are treated like a C Union structure in order to support both the new and old revisions of the EMIF device. Signed-off-by: Debarati Biswas <debaratix.biswas@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220713130355.196115-1-tianfei.zhang@intel.com
2022-07-13 09:03:55 -04:00
memory: dfl-emif: add the DFL EMIF private feature driver This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control. The purpose of memory clearing block is to zero out all private memory when FPGA is to be reprogrammed. This gives users a reliable method to prevent potential data leakage. [mdf@kernel.org: Fixed up ABI doc] Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20210107043714.991646-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-06 20:37:14 -08:00
memory: dfl-emif: Update the dfl emif driver support revision 1 The next generation (revision 1) of the DFL EMIF feature device requires support for more than 4 memory banks. It does not support the selective clearing of memory banks. A capability register replaces the previous control register, and contains a bitmask to indicate the presence of each memory bank. This bitmask aligns with the previous control register bitmask that served the same purpose. The control and capability registers are treated like a C Union structure in order to support both the new and old revisions of the EMIF device. Signed-off-by: Debarati Biswas <debaratix.biswas@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220713130355.196115-1-tianfei.zhang@intel.com
2022-07-13 09:03:55 -04:00
memory: dfl-emif: add the DFL EMIF private feature driver This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control. The purpose of memory clearing block is to zero out all private memory when FPGA is to be reprogrammed. This gives users a reliable method to prevent potential data leakage. [mdf@kernel.org: Fixed up ABI doc] Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20210107043714.991646-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-06 20:37:14 -08:00
memory: dfl-emif: Update the dfl emif driver support revision 1 The next generation (revision 1) of the DFL EMIF feature device requires support for more than 4 memory banks. It does not support the selective clearing of memory banks. A capability register replaces the previous control register, and contains a bitmask to indicate the presence of each memory bank. This bitmask aligns with the previous control register bitmask that served the same purpose. The control and capability registers are treated like a C Union structure in order to support both the new and old revisions of the EMIF device. Signed-off-by: Debarati Biswas <debaratix.biswas@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220713130355.196115-1-tianfei.zhang@intel.com
2022-07-13 09:03:55 -04:00
memory: dfl-emif: add the DFL EMIF private feature driver This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control. The purpose of memory clearing block is to zero out all private memory when FPGA is to be reprogrammed. This gives users a reliable method to prevent potential data leakage. [mdf@kernel.org: Fixed up ABI doc] Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20210107043714.991646-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-01-06 20:37:14 -08:00