2005-04-16 15:20:36 -07:00
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2012-02-28 19:24:47 -05:00
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2016-09-05 11:35:50 -04:00
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2005-04-16 15:20:36 -07:00
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2012-08-08 16:59:43 +02:00
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2005-04-16 15:20:36 -07:00
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2005-02-21 10:45:09 +00:00
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2005-04-16 15:20:36 -07:00
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2005-09-03 15:56:16 -07:00
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2005-04-16 15:20:36 -07:00
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2005-02-21 10:45:09 +00:00
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2012-09-28 14:31:03 +09:30
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2005-02-21 10:45:09 +00:00
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2005-04-16 15:20:36 -07:00
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2005-09-03 15:56:16 -07:00
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2005-04-16 15:20:36 -07:00
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2005-02-21 10:45:09 +00:00
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2012-09-28 14:31:03 +09:30
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2005-02-21 10:45:09 +00:00
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2005-04-16 15:20:36 -07:00
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2011-11-16 01:25:40 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2014-10-27 11:23:34 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2014-10-27 11:23:34 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2008-10-24 01:27:57 +09:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2005-09-12 20:22:07 +00:00
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2005-10-31 00:33:01 +00:00
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2012-06-20 20:05:32 +01:00
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2007-06-06 14:52:43 +08:00
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MIPS: Loongson: Add basic Loongson-3 definition
Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully.
Loongson-3 has the same IMP field (0x6300) as Loongson-2.
Loongson-3 has a hardware-maintained cache, system software doesn't
need to maintain coherency.
Loongson-3A is the first revision of Loongson-3, and it is the quad-
core version of Loongson-2G. Loongson-3A has a simplified version named
Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two
HyperTransport controller but 2Gq has only one. HT0 is used for cross-
chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq
cannot support NUMA but 3A can. For software, Loongson-2Gq is simply
identified as Loongson-3A.
Exsisting Loongson family CPUs:
Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs.
Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit
single-core MIPS CPUs.
Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are
64-bit multi-core MIPS CPUs.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6629/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-03-21 18:43:59 +08:00
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2008-12-11 15:33:26 -08:00
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2011-05-07 01:36:21 +05:30
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2011-11-16 00:21:20 +00:00
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2005-09-12 20:22:07 +00:00
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2007-06-20 14:25:27 +01:00
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2014-05-23 16:29:44 +02:00
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2005-09-12 20:22:07 +00:00
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2005-04-16 15:20:36 -07:00
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