2005-04-16 15:20:36 -07:00
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2008-06-17 12:19:34 +01:00
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2008-04-28 23:44:43 +02:00
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2006-03-27 01:16:35 -08:00
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2007-02-09 17:08:58 +00:00
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2010-01-20 19:05:07 +01:00
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2010-04-30 11:37:51 +01:00
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2008-02-20 13:33:40 -06:00
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2008-02-02 15:10:35 -05:00
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2008-03-04 14:28:37 -08:00
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2008-10-06 19:06:12 -04:00
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2008-07-18 13:30:14 +04:00
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2010-01-08 14:42:43 -08:00
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2010-04-03 11:40:28 +01:00
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2010-02-02 20:24:58 +01:00
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2005-04-16 15:20:36 -07:00
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2006-02-08 21:09:07 +00:00
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2005-04-16 15:20:36 -07:00
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2006-02-08 21:09:07 +00:00
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2005-04-16 15:20:36 -07:00
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2008-04-13 21:41:55 +01:00
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2007-02-09 17:08:58 +00:00
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2007-03-05 00:30:18 -08:00
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2006-09-22 00:16:30 +01:00
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2010-03-24 00:22:36 +00:00
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2006-09-22 00:16:30 +01:00
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2007-03-13 20:29:24 +01:00
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2008-02-04 17:30:57 +01:00
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2009-09-15 17:30:37 +01:00
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2010-01-10 17:23:29 +00:00
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2007-02-11 15:41:31 +00:00
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2005-04-16 15:20:36 -07:00
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2006-07-01 22:30:09 +01:00
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2007-04-28 09:59:37 +01:00
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2008-04-24 01:31:46 -04:00
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2007-04-28 09:59:37 +01:00
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2006-08-27 12:07:02 +01:00
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2006-07-01 22:30:09 +01:00
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2008-01-30 13:31:20 +01:00
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2005-04-16 15:20:36 -07:00
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2006-12-08 02:37:49 -08:00
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2009-07-30 23:23:24 +01:00
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2006-03-26 01:39:19 -08:00
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2005-04-16 15:20:36 -07:00
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2005-09-06 01:48:42 +01:00
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2007-02-10 01:43:14 -08:00
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2010-03-10 15:23:23 -08:00
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2005-04-16 15:20:36 -07:00
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2005-12-19 16:27:59 -05:00
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2008-06-25 13:33:14 +01:00
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2010-02-22 00:02:59 +01:00
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2006-03-27 15:18:50 +01:00
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2006-09-28 21:46:34 +09:00
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2006-03-27 15:18:50 +01:00
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2005-04-16 15:20:36 -07:00
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2008-10-18 20:27:21 -07:00
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2005-04-16 15:20:36 -07:00
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2009-07-24 12:35:00 +01:00
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2010-03-15 19:03:06 +00:00
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2005-04-16 15:20:36 -07:00
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2006-03-07 14:42:27 +00:00
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2005-04-16 15:20:36 -07:00
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2006-06-20 21:30:44 +01:00
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2008-10-26 10:55:14 +00:00
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2006-06-20 21:30:44 +01:00
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2008-07-23 21:26:48 -07:00
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2010-03-24 00:22:36 +00:00
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2006-06-20 21:30:44 +01:00
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2009-07-30 23:23:24 +01:00
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2008-11-08 20:08:08 +00:00
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2010-01-16 20:16:10 +00:00
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2010-01-15 21:49:23 +00:00
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2010-01-14 12:48:06 +00:00
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2006-06-20 21:30:44 +01:00
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2008-11-08 20:05:55 +00:00
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2010-01-16 20:16:10 +00:00
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2008-02-04 17:26:55 +01:00
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2009-07-05 22:41:31 +01:00
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2010-01-14 12:48:06 +00:00
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2010-01-14 13:30:16 +00:00
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2010-02-24 15:23:10 +01:00
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2006-06-20 21:30:44 +01:00
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2008-11-08 20:13:53 +00:00
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2010-01-16 20:16:10 +00:00
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2007-03-08 20:30:38 +01:00
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2009-07-05 22:43:01 +01:00
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2010-01-14 12:48:06 +00:00
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2010-01-14 13:30:16 +00:00
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2006-06-20 21:30:44 +01:00
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2010-02-11 21:44:53 +00:00
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2006-06-29 16:06:33 +01:00
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2009-02-10 21:02:08 +01:00
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2008-07-28 15:46:22 -07:00
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2010-03-24 00:22:36 +00:00
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2006-06-20 21:30:44 +01:00
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2008-01-24 15:10:39 +01:00
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2006-06-20 21:30:44 +01:00
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2010-03-15 19:03:06 +00:00
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2005-04-16 15:20:36 -07:00
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2006-06-20 21:30:44 +01:00
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2008-10-26 10:55:14 +00:00
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2010-03-24 00:22:36 +00:00
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2006-02-08 21:09:05 +00:00
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2005-04-16 15:20:36 -07:00
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2010-03-25 17:12:41 +03:00
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2009-04-26 14:21:59 +01:00
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2010-03-24 00:22:36 +00:00
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2009-04-26 14:21:59 +01:00
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2005-04-16 15:20:36 -07:00
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2008-10-26 10:55:14 +00:00
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2005-05-05 14:49:01 +01:00
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2007-03-03 11:54:19 +00:00
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2010-03-24 00:22:36 +00:00
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2005-04-16 15:20:36 -07:00
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2006-02-08 21:09:07 +00:00
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2005-04-16 15:20:36 -07:00
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[ARM] 3369/1: ep93xx: add core cirrus ep93xx support
Patch from Lennert Buytenhek
This patch adds support for the Cirrus ep93xx series of CPUs. The
ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs,
IrDA, MaverickCrunch floating point coprocessor, between 24 and 64
GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster
engine, graphics accelerator, IDE controller and a bunch of other
stuff.
This patch adds the core ep93xx support code, and support for the
Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-20 17:10:13 +00:00
|
|
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|
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|
|
2008-10-26 10:55:14 +00:00
|
|
|
|
[ARM] 3369/1: ep93xx: add core cirrus ep93xx support
Patch from Lennert Buytenhek
This patch adds support for the Cirrus ep93xx series of CPUs. The
ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs,
IrDA, MaverickCrunch floating point coprocessor, between 24 and 64
GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster
engine, graphics accelerator, IDE controller and a bunch of other
stuff.
This patch adds the core ep93xx support code, and support for the
Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-20 17:10:13 +00:00
|
|
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|
2008-11-30 17:11:49 +00:00
|
|
|
|
2008-07-25 01:46:11 -07:00
|
|
|
|
2009-05-13 17:34:48 +01:00
|
|
|
|
2010-03-24 00:22:36 +00:00
|
|
|
|
[ARM] 3369/1: ep93xx: add core cirrus ep93xx support
Patch from Lennert Buytenhek
This patch adds support for the Cirrus ep93xx series of CPUs. The
ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs,
IrDA, MaverickCrunch floating point coprocessor, between 24 and 64
GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster
engine, graphics accelerator, IDE controller and a bunch of other
stuff.
This patch adds the core ep93xx support code, and support for the
Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-20 17:10:13 +00:00
|
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2005-04-16 15:20:36 -07:00
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2008-10-26 10:55:14 +00:00
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2005-04-16 15:20:36 -07:00
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2010-03-24 00:22:36 +00:00
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2006-02-08 21:09:05 +00:00
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2005-04-16 15:20:36 -07:00
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2009-04-26 14:21:59 +01:00
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2010-02-15 17:10:42 +01:00
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2009-04-26 14:21:59 +01:00
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2009-04-27 10:35:04 +01:00
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2006-06-20 21:30:44 +01:00
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2008-10-26 10:55:14 +00:00
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2006-06-20 21:30:44 +01:00
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2008-12-09 21:57:24 +01:00
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2006-02-08 21:09:05 +00:00
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2006-06-20 21:30:44 +01:00
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2008-10-26 10:55:14 +00:00
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2006-06-20 21:30:44 +01:00
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2010-03-24 00:22:36 +00:00
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2006-06-20 21:30:44 +01:00
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2007-05-12 11:25:44 +01:00
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2008-10-26 10:55:14 +00:00
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2007-05-12 11:25:44 +01:00
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2008-08-25 21:03:32 +01:00
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2007-05-12 11:25:44 +01:00
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2006-09-18 23:10:26 +01:00
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2006-06-28 12:52:41 +01:00
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2008-10-26 10:55:14 +00:00
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2006-09-18 23:12:53 +01:00
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2005-05-05 14:49:01 +01:00
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2008-07-26 15:36:03 +01:00
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2006-02-08 21:09:05 +00:00
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2006-09-18 23:10:26 +01:00
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2008-10-26 10:55:14 +00:00
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2006-09-18 23:12:53 +01:00
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2006-09-18 23:10:26 +01:00
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2008-07-26 15:36:03 +01:00
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2006-09-18 23:10:26 +01:00
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2005-04-16 15:20:36 -07:00
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2007-05-12 11:25:44 +01:00
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2006-06-28 12:52:41 +01:00
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2008-10-26 10:55:14 +00:00
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2007-05-12 11:25:44 +01:00
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2010-03-24 00:22:36 +00:00
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2006-02-08 21:09:05 +00:00
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2007-05-12 11:25:44 +01:00
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2005-04-16 15:20:36 -07:00
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2006-06-28 12:52:41 +01:00
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2008-10-26 10:55:14 +00:00
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2005-05-05 14:49:01 +01:00
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2010-03-24 00:22:36 +00:00
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2006-02-08 21:09:05 +00:00
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2005-04-16 15:20:36 -07:00
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2007-05-12 11:25:44 +01:00
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2006-06-28 12:52:41 +01:00
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2008-10-26 10:55:14 +00:00
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2007-05-14 07:50:42 +01:00
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2007-05-12 11:25:44 +01:00
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2008-10-17 14:00:43 +01:00
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[ARM] 3388/1: ixp23xx: add core ixp23xx support
Patch from Lennert Buytenhek
This patch adds support for the Intel ixp23xx series of CPUs. The
ixp23xx is an XSC3 based CPU with 512K of L2 cache, a 64bit 66MHz PCI
interface, two DDR RAM interfaces, QDR RAM interfaces, two gigabit
MACs, two 10/100 MACs, expansion bus, four microengines, a Media and
Switch Fabric unit almost identical to the one on the ixp2400, two
xscale (8250ish) UARTs and a bunch of other stuff.
This patch adds the core ixp23xx support code, and support for the
ADI Engineering Roadrunner, Intel IXDP2351, and IP Fabrics Double
Espresso platforms.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-28 21:18:54 +01:00
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2007-05-12 11:25:44 +01:00
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|
[ARM] 3388/1: ixp23xx: add core ixp23xx support
Patch from Lennert Buytenhek
This patch adds support for the Intel ixp23xx series of CPUs. The
ixp23xx is an XSC3 based CPU with 512K of L2 cache, a 64bit 66MHz PCI
interface, two DDR RAM interfaces, QDR RAM interfaces, two gigabit
MACs, two 10/100 MACs, expansion bus, four microengines, a Media and
Switch Fabric unit almost identical to the one on the ixp2400, two
xscale (8250ish) UARTs and a bunch of other stuff.
This patch adds the core ixp23xx support code, and support for the
ADI Engineering Roadrunner, Intel IXDP2351, and IP Fabrics Double
Espresso platforms.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-28 21:18:54 +01:00
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2005-04-16 15:20:36 -07:00
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2008-10-26 10:55:14 +00:00
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2005-04-16 15:20:36 -07:00
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2010-03-24 00:22:36 +00:00
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2005-04-16 15:20:36 -07:00
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2009-08-06 15:12:43 +03:00
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[ARM] add Marvell Kirkwood (88F6000) SoC support
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.
This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:06 +02:00
|
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|
|
2008-10-26 10:55:14 +00:00
|
|
|
|
[ARM] add Marvell Kirkwood (88F6000) SoC support
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.
This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:06 +02:00
|
|
|
|
2009-05-28 17:08:55 -07:00
|
|
|
|
[ARM] add Marvell Kirkwood (88F6000) SoC support
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.
This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:06 +02:00
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[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:02 +02:00
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|
|
2008-10-26 10:55:14 +00:00
|
|
|
|
[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:02 +02:00
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|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:10 +02:00
|
|
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|
|
2008-10-26 10:55:14 +00:00
|
|
|
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:10 +02:00
|
|
|
|
2009-05-28 17:08:55 -07:00
|
|
|
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:10 +02:00
|
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|
2008-03-27 14:51:41 -04:00
|
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|
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
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|
|
|
2008-10-26 10:55:14 +00:00
|
|
|
|
2007-10-23 15:14:42 -04:00
|
|
|
|
2009-05-28 17:08:55 -07:00
|
|
|
|
2007-10-23 15:14:42 -04:00
|
|
|
|
2008-03-27 14:51:39 -04:00
|
|
|
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
|
2008-05-31 08:30:40 +02:00
|
|
|
|
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-29 06:55:06 +02:00
|
|
|
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
|
2009-04-26 14:21:59 +01:00
|
|
|
|
2009-12-04 09:41:28 -05:00
|
|
|
|
2009-04-26 14:21:59 +01:00
|
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|
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|
|
|
2009-12-04 09:41:28 -05:00
|
|
|
|
2009-04-26 14:21:59 +01:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2010-05-17 17:18:10 +01:00
|
|
|
|
2010-03-24 00:22:36 +00:00
|
|
|
|
2009-04-26 14:21:59 +01:00
|
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2009-06-10 15:49:32 +01:00
|
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|
2009-06-10 15:50:44 +01:00
|
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|
2009-08-14 15:36:44 +01:00
|
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2009-04-26 14:21:59 +01:00
|
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2009-08-14 15:38:29 +01:00
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2009-04-26 14:21:59 +01:00
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2009-12-31 15:06:05 +01:00
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2006-06-20 21:30:44 +01:00
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2008-10-26 10:55:14 +00:00
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2009-11-20 10:32:41 +00:00
|
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2010-03-24 00:22:36 +00:00
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2006-06-20 21:30:44 +01:00
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2005-04-16 15:20:36 -07:00
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2007-09-11 19:13:17 -07:00
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2006-06-28 12:52:41 +01:00
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2005-12-19 16:27:59 -05:00
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2009-07-30 23:23:24 +01:00
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2008-11-08 20:25:21 +00:00
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2008-07-25 01:46:11 -07:00
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2007-07-24 01:22:43 +01:00
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2007-11-12 22:45:16 +00:00
|
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2009-01-20 12:06:01 +08:00
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2006-02-08 21:09:05 +00:00
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2007-09-11 19:13:17 -07:00
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2005-04-16 15:20:36 -07:00
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2009-04-26 14:21:59 +01:00
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2008-12-29 16:17:22 -05:00
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2009-01-20 14:15:18 +08:00
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2010-01-01 15:11:43 -08:00
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2009-01-20 14:15:18 +08:00
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2010-02-05 11:14:49 +00:00
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2005-04-16 15:20:36 -07:00
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2005-09-06 01:48:42 +01:00
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2008-07-01 14:16:49 +01:00
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2006-01-04 15:44:16 +00:00
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2007-02-11 15:41:31 +00:00
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2008-10-01 17:11:06 +01:00
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2010-03-24 00:22:36 +00:00
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2005-04-16 15:20:36 -07:00
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2008-10-26 10:55:14 +00:00
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2005-05-05 14:49:01 +01:00
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2006-11-30 20:43:51 +00:00
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2005-12-19 16:27:59 -05:00
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2009-07-30 23:23:24 +01:00
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2009-12-12 16:20:57 +00:00
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2008-04-14 23:03:10 +01:00
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2008-07-23 21:26:48 -07:00
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2008-04-14 23:03:10 +01:00
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2008-07-25 01:46:11 -07:00
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2006-02-08 21:09:05 +00:00
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2005-04-16 15:20:36 -07:00
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2010-04-30 16:32:26 +09:00
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2007-03-05 00:30:18 -08:00
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2009-07-30 23:23:25 +01:00
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2008-07-23 21:26:48 -07:00
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2010-03-24 00:22:36 +00:00
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2005-04-16 15:20:36 -07:00
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2006-02-08 21:09:07 +00:00
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2005-04-16 15:20:36 -07:00
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2010-04-30 16:32:26 +09:00
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2008-10-21 14:06:39 +01:00
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2010-01-29 09:02:17 +00:00
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2010-01-26 15:49:15 +09:00
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2008-10-21 14:06:39 +01:00
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2010-01-26 15:49:15 +09:00
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2010-03-24 00:22:36 +00:00
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2009-07-30 23:23:24 +01:00
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2010-01-26 15:49:15 +09:00
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2008-10-21 14:06:39 +01:00
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2010-01-14 08:19:36 +09:00
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2010-05-20 20:48:28 +09:00
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2010-01-14 08:19:36 +09:00
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2010-01-29 10:19:26 +09:00
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2010-05-20 20:48:28 +09:00
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2010-01-29 10:19:26 +09:00
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2010-05-20 07:51:08 +02:00
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2009-06-23 21:39:42 +09:00
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2010-02-22 00:02:59 +01:00
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2010-05-20 20:48:28 +09:00
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2009-06-23 21:39:42 +09:00
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2010-05-20 07:51:08 +02:00
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2009-06-23 21:39:42 +09:00
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2010-02-24 16:40:44 +09:00
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2010-05-20 20:48:28 +09:00
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2010-02-24 16:40:44 +09:00
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2005-04-16 15:20:36 -07:00
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2008-10-26 10:55:14 +00:00
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2005-05-05 14:49:01 +01:00
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2008-10-07 20:14:55 +01:00
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2005-05-05 14:49:01 +01:00
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2010-03-24 00:22:36 +00:00
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2006-02-08 21:09:05 +00:00
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2005-04-16 15:20:36 -07:00
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2008-10-26 10:55:14 +00:00
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2008-10-01 21:38:23 +01:00
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2010-03-24 00:22:36 +00:00
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2005-04-16 15:20:36 -07:00
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2009-04-27 10:21:46 +01:00
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2009-09-15 17:30:37 +01:00
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2009-04-27 10:21:46 +01:00
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2010-03-15 19:03:06 +00:00
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2010-03-03 04:54:37 +01:00
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2010-03-15 19:03:06 +00:00
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2007-04-30 19:37:19 +01:00
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2008-09-07 23:41:04 -07:00
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2008-10-07 20:14:55 +01:00
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2009-04-08 14:49:38 -07:00
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2009-03-20 17:29:01 -07:00
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2009-05-07 09:31:42 -07:00
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2009-11-19 15:34:01 +05:30
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2007-04-30 19:37:19 +01:00
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2007-05-12 11:25:44 +01:00
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2008-07-23 21:26:48 -07:00
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2008-07-25 01:46:11 -07:00
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2009-07-30 23:23:24 +01:00
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2007-10-18 23:04:43 -07:00
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2010-01-29 14:20:05 -08:00
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2007-05-12 11:25:44 +01:00
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2010-04-01 12:31:05 +01:00
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2005-04-16 15:20:36 -07:00
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2010-03-15 19:03:06 +00:00
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2010-01-14 11:43:54 +00:00
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2005-04-16 15:20:36 -07:00
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2010-03-25 17:12:41 +03:00
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2010-01-14 11:43:54 +00:00
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[ARM] 3369/1: ep93xx: add core cirrus ep93xx support
Patch from Lennert Buytenhek
This patch adds support for the Cirrus ep93xx series of CPUs. The
ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs,
IrDA, MaverickCrunch floating point coprocessor, between 24 and 64
GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster
engine, graphics accelerator, IDE controller and a bunch of other
stuff.
This patch adds the core ep93xx support code, and support for the
Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-20 17:10:13 +00:00
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2005-04-16 15:20:36 -07:00
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2009-03-26 10:06:08 +02:00
|
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2010-01-14 11:43:54 +00:00
|
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2005-04-16 15:20:36 -07:00
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2006-09-18 23:10:26 +01:00
|
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2005-04-16 15:20:36 -07:00
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2006-12-07 02:59:39 +01:00
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2005-04-16 15:20:36 -07:00
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|
[ARM] 3388/1: ixp23xx: add core ixp23xx support
Patch from Lennert Buytenhek
This patch adds support for the Intel ixp23xx series of CPUs. The
ixp23xx is an XSC3 based CPU with 512K of L2 cache, a 64bit 66MHz PCI
interface, two DDR RAM interfaces, QDR RAM interfaces, two gigabit
MACs, two 10/100 MACs, expansion bus, four microengines, a Media and
Switch Fabric unit almost identical to the one on the ixp2400, two
xscale (8250ish) UARTs and a bunch of other stuff.
This patch adds the core ixp23xx support code, and support for the
ADI Engineering Roadrunner, Intel IXDP2351, and IP Fabrics Double
Espresso platforms.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-28 21:18:54 +01:00
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|
2010-01-14 11:43:54 +00:00
|
|
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|
[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:02 +02:00
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2010-01-14 11:43:54 +00:00
|
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|
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|
|
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:10 +02:00
|
|
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|
|
2010-01-14 11:43:54 +00:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2010-01-14 11:43:54 +00:00
|
|
|
|
2009-01-20 14:15:18 +08:00
|
|
|
|
2010-01-14 11:43:54 +00:00
|
|
|
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|
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2010-02-25 22:07:25 +00:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2005-07-10 19:58:17 +01:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2005-11-10 14:26:51 +00:00
|
|
|
|
|
|
|
|
|
2008-03-27 14:51:41 -04:00
|
|
|
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
|
2010-01-14 11:43:54 +00:00
|
|
|
|
|
|
|
|
|
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 15:14:41 -04:00
|
|
|
|
2010-01-14 11:43:54 +00:00
|
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|
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|
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|
|
|
2009-08-06 15:12:43 +03:00
|
|
|
|
2009-11-10 00:14:58 +00:00
|
|
|
|
2007-02-11 18:31:01 +01:00
|
|
|
|
2010-01-14 08:19:36 +09:00
|
|
|
|
2007-02-11 18:31:01 +01:00
|
|
|
|
2010-04-01 12:31:05 +01:00
|
|
|
|
2007-02-11 18:31:01 +01:00
|
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|
2005-04-16 15:20:36 -07:00
|
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|
|
2007-02-11 18:31:01 +01:00
|
|
|
|
2010-04-28 18:09:01 +09:00
|
|
|
|
2007-02-11 18:31:01 +01:00
|
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|
2007-02-16 12:12:31 +01:00
|
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|
2007-02-11 18:31:01 +01:00
|
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2005-04-16 15:20:36 -07:00
|
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|
2008-10-21 14:06:39 +01:00
|
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|
|
2010-01-26 10:11:04 +09:00
|
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|
2008-10-21 14:06:39 +01:00
|
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|
2010-01-14 08:19:36 +09:00
|
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2010-01-29 10:19:26 +09:00
|
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|
2009-04-27 10:35:04 +01:00
|
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|
2009-06-23 21:39:42 +09:00
|
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|
2010-02-24 16:40:44 +09:00
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2010-03-02 23:40:15 +00:00
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2007-07-09 22:06:53 +01:00
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2010-03-02 23:40:15 +00:00
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2007-11-26 04:12:13 -08:00
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2010-01-14 11:43:54 +00:00
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2005-04-16 15:20:36 -07:00
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2010-01-14 11:43:54 +00:00
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2005-04-16 15:20:36 -07:00
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2010-02-11 21:44:53 +00:00
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2008-12-03 03:55:38 +01:00
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2005-04-16 15:20:36 -07:00
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2006-09-18 23:12:53 +01:00
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2009-10-29 11:46:54 -07:00
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2006-09-18 23:12:53 +01:00
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2008-03-27 14:51:39 -04:00
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2009-01-20 12:06:01 +08:00
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2010-01-14 12:48:06 +00:00
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2010-01-14 13:30:16 +00:00
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2005-04-16 15:20:36 -07:00
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[ARM] 3881/4: xscale: clean up cp0/cp1 handling
XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)
Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch. Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.
CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.
This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.' This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.
These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-03 18:51:14 +01:00
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2009-02-26 09:34:35 +08:00
|
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|
|
|
[ARM] 3881/4: xscale: clean up cp0/cp1 handling
XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)
Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch. Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.
CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.
This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.' This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.
These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-03 18:51:14 +01:00
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2005-04-16 15:20:36 -07:00
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2010-02-02 20:23:15 +01:00
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|
2010-06-21 15:32:54 +01:00
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2010-02-02 20:23:15 +01:00
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2006-06-22 11:48:56 +01:00
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2009-04-30 17:06:03 +01:00
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2009-04-30 17:06:09 +01:00
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2009-04-30 17:06:15 +01:00
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2009-04-30 17:06:20 +01:00
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2010-02-04 19:42:42 +01:00
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2005-04-16 15:20:36 -07:00
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2006-01-04 15:44:16 +00:00
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2005-04-16 15:20:36 -07:00
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2006-01-04 15:44:16 +00:00
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2005-04-16 15:20:36 -07:00
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2006-01-04 15:44:16 +00:00
|
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2005-05-04 05:39:22 +01:00
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2005-04-16 15:20:36 -07:00
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2007-11-25 08:55:34 +01:00
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2005-04-16 15:20:36 -07:00
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2010-04-19 13:20:49 +01:00
|
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2007-07-10 10:54:40 -06:00
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2005-04-16 15:20:36 -07:00
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2007-11-25 08:55:34 +01:00
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2005-04-16 15:20:36 -07:00
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2007-03-13 20:29:24 +01:00
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2005-04-16 15:20:36 -07:00
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2009-06-11 15:35:00 +01:00
|
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|
2010-02-11 21:56:07 +00:00
|
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|
2009-05-17 18:58:34 +01:00
|
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|
2008-06-10 20:48:30 +02:00
|
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|
|
2010-02-11 21:56:07 +00:00
|
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|
2005-04-16 15:20:36 -07:00
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2008-02-03 15:50:21 +02:00
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2005-04-16 15:20:36 -07:00
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2009-05-16 11:51:14 +01:00
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2009-05-16 12:14:21 +01:00
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2008-08-25 21:03:32 +01:00
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2005-04-16 15:20:36 -07:00
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2005-11-02 22:24:33 +00:00
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2005-11-08 19:08:05 +00:00
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2009-06-11 15:35:00 +01:00
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|
2009-11-28 08:24:47 +01:00
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|
2005-11-08 19:08:05 +00:00
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2009-11-28 08:24:47 +01:00
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2005-11-08 19:08:05 +00:00
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2009-08-13 20:38:17 +02:00
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2005-04-16 15:20:36 -07:00
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|
2006-03-02 22:41:59 +00:00
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2010-02-24 16:40:44 +09:00
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2006-03-04 11:01:53 +00:00
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|
2007-11-12 17:59:10 +01:00
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2006-03-02 22:41:59 +00:00
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2009-07-24 12:33:02 +01:00
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2009-07-24 12:32:53 +01:00
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2006-01-14 16:33:50 +00:00
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2006-01-14 16:37:15 +00:00
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2006-02-08 21:09:55 +00:00
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2006-02-08 21:09:08 +00:00
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2006-01-14 16:37:15 +00:00
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2009-05-13 17:34:48 +01:00
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|
2008-08-14 11:10:14 +01:00
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2008-10-01 21:39:58 +01:00
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2005-06-23 00:07:43 -07:00
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2005-04-16 15:20:36 -07:00
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2006-11-30 20:43:51 +00:00
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2008-10-01 21:39:58 +01:00
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2006-11-30 20:43:51 +00:00
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2008-10-01 21:39:58 +01:00
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2006-11-30 20:43:51 +00:00
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2006-04-10 22:53:53 -07:00
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2008-09-19 00:36:12 -04:00
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2009-08-17 20:02:06 +01:00
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2010-02-02 20:25:44 +01:00
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2010-04-30 11:37:51 +01:00
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2010-02-02 20:25:44 +01:00
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2005-06-23 00:07:43 -07:00
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2005-04-16 15:20:36 -07:00
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2008-04-22 01:43:27 +01:00
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2009-04-01 12:40:15 +02:00
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2005-04-16 15:20:36 -07:00
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2006-01-09 17:05:41 +00:00
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2008-09-16 21:36:30 +01:00
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2009-05-30 13:56:13 +01:00
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2005-04-16 15:20:36 -07:00
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2007-04-02 12:48:10 -07:00
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2005-04-16 15:20:36 -07:00
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2007-03-13 20:29:24 +01:00
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2005-04-16 15:20:36 -07:00
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2007-04-02 12:48:10 -07:00
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2005-04-16 15:20:36 -07:00
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2006-09-26 17:36:37 +09:00
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2005-04-16 15:20:36 -07:00
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2010-01-10 17:23:29 +00:00
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2005-04-16 15:20:36 -07:00
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2006-10-03 22:53:09 +02:00
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2005-04-16 15:20:36 -07:00
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2009-03-09 14:30:09 -04:00
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2005-04-16 15:20:36 -07:00
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2006-09-20 23:28:51 +01:00
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2005-04-16 15:20:36 -07:00
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2010-02-16 19:04:53 +01:00
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2005-04-16 15:20:36 -07:00
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2007-02-06 21:29:00 +01:00
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2007-10-20 01:34:40 +02:00
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2007-02-06 21:29:00 +01:00
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2008-01-02 00:56:46 +01:00
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2008-02-22 16:45:18 +01:00
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2008-01-02 00:56:46 +01:00
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2005-04-16 15:20:36 -07:00
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2008-08-18 17:26:00 +01:00
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2005-04-16 15:20:36 -07:00
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2009-07-30 23:23:24 +01:00
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2005-04-16 15:20:36 -07:00
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2007-12-14 13:30:14 +00:00
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2009-06-15 11:23:20 +01:00
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2009-07-30 23:23:25 +01:00
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2009-07-30 23:23:42 +01:00
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2005-04-16 15:20:36 -07:00
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2008-08-18 17:26:00 +01:00
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2005-04-16 15:20:36 -07:00
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2006-01-14 16:36:50 +00:00
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2005-04-16 15:20:36 -07:00
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2005-11-07 21:12:08 +00:00
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2005-04-16 15:20:36 -07:00
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2006-01-14 16:36:50 +00:00
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2005-04-16 15:20:36 -07:00
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2008-01-28 13:21:30 +00:00
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2005-04-16 15:20:36 -07:00
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2007-09-25 15:22:24 +01:00
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2008-01-10 19:16:17 +01:00
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2005-04-16 15:20:36 -07:00
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2006-01-14 16:33:50 +00:00
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2005-04-16 15:20:36 -07:00
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2005-11-15 11:31:41 +00:00
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2005-04-16 15:20:36 -07:00
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2007-12-08 02:14:00 +01:00
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2005-04-16 15:20:36 -07:00
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2005-07-11 21:03:49 -07:00
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2009-08-13 21:09:21 +02:00
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2005-04-16 15:20:36 -07:00
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