2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-11-10 13:37:51 +11:00
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2005-04-16 15:20:36 -07:00
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2005-11-10 13:37:51 +11:00
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2005-04-16 15:20:36 -07:00
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2005-11-10 13:37:51 +11:00
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2005-04-16 15:20:36 -07:00
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2006-07-04 14:16:28 +10:00
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2005-04-16 15:20:36 -07:00
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2006-03-28 23:15:54 +11:00
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2005-11-10 13:37:51 +11:00
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2006-03-28 10:22:10 +11:00
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2005-11-10 13:37:51 +11:00
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2005-04-16 15:20:36 -07:00
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2005-11-10 13:37:51 +11:00
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2005-04-16 15:20:36 -07:00
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2005-11-10 13:37:51 +11:00
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2006-03-28 10:22:10 +11:00
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2006-03-28 23:15:54 +11:00
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2005-04-16 15:20:36 -07:00
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2006-03-28 23:15:54 +11:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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[PATCH] powerpc: Fix handling of fpscr on 64-bit
The recent merge of fpu.S broken the handling of fpscr for
ARCH=powerpc and CONFIG_PPC64=y. FP registers could be corrupted,
leading to strange random application crashes.
The confusion arises, because the thread_struct has (and requires) a
64-bit area to save the fpscr, because we use load/store double
instructions to get it in to/out of the FPU. However, only the low
32-bits are actually used, so we want to treat it as a 32-bit quantity
when manipulating its bits to avoid extra load/stores on 32-bit. This
patch replaces the current definition with a structure of two 32-bit
quantities (pad and val), to clarify things as much as is possible.
The 'val' field is used when manipulating bits, the structure itself
is used when obtaining the address for loading/unloading the value
from the FPU.
While we're at it, consolidate the 4 (!) almost identical versions of
cvt_fd() and cvt_df() (arch/ppc/kernel/misc.S,
arch/ppc64/kernel/misc.S, arch/powerpc/kernel/misc_32.S,
arch/powerpc/kernel/misc_64.S) into a single version in fpu.S. The
new version takes a pointer to thread_struct and applies the correct
offset itself, rather than a pointer to the fpscr field itself, again
to avoid confusion as to which is the correct field to use.
Finally, this patch makes ARCH=ppc64 also use the consolidated fpu.S
code, which it previously did not.
Built for G5 (ARCH=ppc64 and ARCH=powerpc), 32-bit powermac (ARCH=ppc
and ARCH=powerpc) and Walnut (ARCH=ppc, CONFIG_MATH_EMULATION=y).
Booted on G5 (ARCH=powerpc) and things which previously fell over no
longer do.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-10-27 16:27:25 +10:00
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2005-10-10 14:19:43 +10:00
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2006-06-07 16:15:39 +10:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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[PATCH] powerpc: Fix handling of fpscr on 64-bit
The recent merge of fpu.S broken the handling of fpscr for
ARCH=powerpc and CONFIG_PPC64=y. FP registers could be corrupted,
leading to strange random application crashes.
The confusion arises, because the thread_struct has (and requires) a
64-bit area to save the fpscr, because we use load/store double
instructions to get it in to/out of the FPU. However, only the low
32-bits are actually used, so we want to treat it as a 32-bit quantity
when manipulating its bits to avoid extra load/stores on 32-bit. This
patch replaces the current definition with a structure of two 32-bit
quantities (pad and val), to clarify things as much as is possible.
The 'val' field is used when manipulating bits, the structure itself
is used when obtaining the address for loading/unloading the value
from the FPU.
While we're at it, consolidate the 4 (!) almost identical versions of
cvt_fd() and cvt_df() (arch/ppc/kernel/misc.S,
arch/ppc64/kernel/misc.S, arch/powerpc/kernel/misc_32.S,
arch/powerpc/kernel/misc_64.S) into a single version in fpu.S. The
new version takes a pointer to thread_struct and applies the correct
offset itself, rather than a pointer to the fpscr field itself, again
to avoid confusion as to which is the correct field to use.
Finally, this patch makes ARCH=ppc64 also use the consolidated fpu.S
code, which it previously did not.
Built for G5 (ARCH=ppc64 and ARCH=powerpc), 32-bit powermac (ARCH=ppc
and ARCH=powerpc) and Walnut (ARCH=ppc, CONFIG_MATH_EMULATION=y).
Booted on G5 (ARCH=powerpc) and things which previously fell over no
longer do.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-10-27 16:27:25 +10:00
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[POWERPC] disable floating point exceptions for init
Floating point exceptions should not be enabled by default,
as this setting impacts the performance on some CPUs, in
particular the Cell BE. Since the bits are inherited from
parent processes, the place to change the default is the
thread struct used for init.
glibc sets this up correctly per thread in its fesetenv
function, so user space should not be impacted by this
setting. None of the other common libc implementations
(uClibc, dietlibc, newlib, klibc) has support for fp
exceptions, so they are unlikely to be hit by this either.
There is a small risk that somebody wrote their own
application that manually sets the fpscr bits instead
of calling fesetenv, without changing the MSR bits as well.
Those programs will break with this change.
It probably makes sense to change glibc in the future
to be more clever about FE bits, so that when running
on a CPU where this is expensive, it disables exceptions
ASAP, while it keeps them enabled on CPUs where running
with exceptions on is cheaper than changing the state
often.
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-06-20 02:30:33 +02:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2006-06-07 16:14:40 +10:00
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2006-06-07 16:15:39 +10:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2006-03-27 11:46:18 +11:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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2005-04-16 15:20:36 -07:00
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2005-10-10 14:19:43 +10:00
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