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linux/include/asm-xtensa/processor.h

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[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 22:01:26 -07:00
[PATCH] xtensa: remove extra header files The Xtensa port contained many header files that were never needed. This rather lengthy patch removes all those files. Unfortunately, there were many dependencies that needed to be updated, so this patch touches quite a few source files. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-12-10 02:18:48 -08:00
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 22:01:26 -07:00
[PATCH] Make cpu_relax() imply barrier() on all arches During the recent discussion of taking 'volatile' off of the spinlock, I noticed that while most arches #define cpu_relax() such that it implies barrier(), some arches define cpu_relax() to be empty. This patch changes the definition of cpu_relax() for frv, h8300, m68knommu, sh, sh64, v850 and xtensa from an empty while(0) to the compiler barrier(). Signed-off-by: Chase Venters <chase.venters@clientec.com> Acked-by: Arjan van de Ven <arjan@Linux.intel.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-07-08 11:10:29 -05:00
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 22:01:26 -07:00
[PATCH] xtensa: remove extra header files The Xtensa port contained many header files that were never needed. This rather lengthy patch removes all those files. Unfortunately, there were many dependencies that needed to be updated, so this patch touches quite a few source files. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-12-10 02:18:48 -08:00
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 22:01:26 -07:00
[PATCH] xtensa: remove extra header files The Xtensa port contained many header files that were never needed. This rather lengthy patch removes all those files. Unfortunately, there were many dependencies that needed to be updated, so this patch touches quite a few source files. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-12-10 02:18:48 -08:00
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 22:01:26 -07:00
[XTENSA] Add typecast macro for constants Add macros (__XTENSA_UL and __XTENSA_UL_CONST) for typecasting constants. Signed-off-by: Chris Zankel <chris@zankel.net>
2007-08-05 11:24:13 -07:00
aout: move STACK_TOP[_MAX] to asm/processor.h Move STACK_TOP[_MAX] out of asm/a.out.h and into asm/processor.h as they're required whether or not A.OUT format is available. Signed-off-by: David Howells <dhowells@redhat.com> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-02-08 04:19:26 -08:00
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 22:01:26 -07:00
[PATCH] xtensa: remove extra header files The Xtensa port contained many header files that were never needed. This rather lengthy patch removes all those files. Unfortunately, there were many dependencies that needed to be updated, so this patch touches quite a few source files. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-12-10 02:18:48 -08:00
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 22:01:26 -07:00
[XTENSA] Add support for configurable registers and coprocessors The Xtensa architecture allows to define custom instructions and registers. Registers that are bound to a coprocessor are only accessible if the corresponding enable bit is set, which allows to implement a 'lazy' context switch mechanism. Other registers needs to be saved and restore at the time of the context switch or during interrupt handling. This patch adds support for these additional states: - save and restore registers that are used by the compiler upon interrupt entry and exit. - context switch additional registers unbound to any coprocessor - 'lazy' context switch of registers bound to a coprocessor - ptrace interface to provide access to additional registers - update configuration files in include/asm-xtensa/variant-fsf Signed-off-by: Chris Zankel <chris@zankel.net>
2008-02-12 13:17:07 -08:00
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 22:01:26 -07:00
[XTENSA] Add support for configurable registers and coprocessors The Xtensa architecture allows to define custom instructions and registers. Registers that are bound to a coprocessor are only accessible if the corresponding enable bit is set, which allows to implement a 'lazy' context switch mechanism. Other registers needs to be saved and restore at the time of the context switch or during interrupt handling. This patch adds support for these additional states: - save and restore registers that are used by the compiler upon interrupt entry and exit. - context switch additional registers unbound to any coprocessor - 'lazy' context switch of registers bound to a coprocessor - ptrace interface to provide access to additional registers - update configuration files in include/asm-xtensa/variant-fsf Signed-off-by: Chris Zankel <chris@zankel.net>
2008-02-12 13:17:07 -08:00
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 22:01:26 -07:00
[PATCH] xtensa: task_pt_regs(), task_stack_page() Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 01:05:50 -08:00
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 22:01:26 -07:00
[PATCH] xtensa: task_pt_regs(), task_stack_page() Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 01:05:50 -08:00
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 22:01:26 -07:00
[PATCH] Make cpu_relax() imply barrier() on all arches During the recent discussion of taking 'volatile' off of the spinlock, I noticed that while most arches #define cpu_relax() such that it implies barrier(), some arches define cpu_relax() to be empty. This patch changes the definition of cpu_relax() for frv, h8300, m68knommu, sh, sh64, v850 and xtensa from an empty while(0) to the compiler barrier(). Signed-off-by: Chase Venters <chase.venters@clientec.com> Acked-by: Arjan van de Ven <arjan@Linux.intel.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-07-08 11:10:29 -05:00
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6 The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-23 22:01:26 -07:00