linux/drivers/gpio/Kconfig

1950 lines
57 KiB

gpio: sysfs interface This adds a simple sysfs interface for GPIOs. /sys/class/gpio /export ... asks the kernel to export a GPIO to userspace /unexport ... to return a GPIO to the kernel /gpioN ... for each exported GPIO #N /value ... always readable, writes fail for input GPIOs /direction ... r/w as: in, out (default low); write high, low /gpiochipN ... for each gpiochip; #N is its first GPIO /base ... (r/o) same as N /label ... (r/o) descriptive, not necessarily unique /ngpio ... (r/o) number of GPIOs; numbered N .. N+(ngpio - 1) GPIOs claimed by kernel code may be exported by its owner using a new gpio_export() call, which should be most useful for driver debugging. Such exports may optionally be done without a "direction" attribute. Userspace may ask to take over a GPIO by writing to a sysfs control file, helping to cope with incomplete board support or other "one-off" requirements that don't merit full kernel support: echo 23 > /sys/class/gpio/export ... will gpio_request(23, "sysfs") and gpio_export(23); use /sys/class/gpio/gpio-23/direction to (re)configure it, when that GPIO can be used as both input and output. echo 23 > /sys/class/gpio/unexport ... will gpio_free(23), when it was exported as above The extra D-space footprint is a few hundred bytes, except for the sysfs resources associated with each exported GPIO. The additional I-space footprint is about two thirds of the current size of gpiolib (!). Since no /dev node creation is involved, no "udev" support is needed. Related changes: * This adds a device pointer to "struct gpio_chip". When GPIO providers initialize that, sysfs gpio class devices become children of that device instead of being "virtual" devices. * The (few) gpio_chip providers which have such a device node have been updated. * Some gpio_chip drivers also needed to update their module "owner" field ... for which missing kerneldoc was added. * Some gpio_chips don't support input GPIOs. Those GPIOs are now flagged appropriately when the chip is registered. Based on previous patches, and discussion both on and off LKML. A Documentation/ABI/testing/sysfs-gpio update is ready to submit once this merges to mainline. [akpm@linux-foundation.org: a few maintenance build fixes] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Cc: Guennadi Liakhovetski <g.liakhovetski@pengutronix.de> Cc: Greg KH <greg@kroah.com> Cc: Kay Sievers <kay.sievers@vrfy.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-07-25 01:46:07 -07:00
gpio: sysfs interface This adds a simple sysfs interface for GPIOs. /sys/class/gpio /export ... asks the kernel to export a GPIO to userspace /unexport ... to return a GPIO to the kernel /gpioN ... for each exported GPIO #N /value ... always readable, writes fail for input GPIOs /direction ... r/w as: in, out (default low); write high, low /gpiochipN ... for each gpiochip; #N is its first GPIO /base ... (r/o) same as N /label ... (r/o) descriptive, not necessarily unique /ngpio ... (r/o) number of GPIOs; numbered N .. N+(ngpio - 1) GPIOs claimed by kernel code may be exported by its owner using a new gpio_export() call, which should be most useful for driver debugging. Such exports may optionally be done without a "direction" attribute. Userspace may ask to take over a GPIO by writing to a sysfs control file, helping to cope with incomplete board support or other "one-off" requirements that don't merit full kernel support: echo 23 > /sys/class/gpio/export ... will gpio_request(23, "sysfs") and gpio_export(23); use /sys/class/gpio/gpio-23/direction to (re)configure it, when that GPIO can be used as both input and output. echo 23 > /sys/class/gpio/unexport ... will gpio_free(23), when it was exported as above The extra D-space footprint is a few hundred bytes, except for the sysfs resources associated with each exported GPIO. The additional I-space footprint is about two thirds of the current size of gpiolib (!). Since no /dev node creation is involved, no "udev" support is needed. Related changes: * This adds a device pointer to "struct gpio_chip". When GPIO providers initialize that, sysfs gpio class devices become children of that device instead of being "virtual" devices. * The (few) gpio_chip providers which have such a device node have been updated. * Some gpio_chip drivers also needed to update their module "owner" field ... for which missing kerneldoc was added. * Some gpio_chips don't support input GPIOs. Those GPIOs are now flagged appropriately when the chip is registered. Based on previous patches, and discussion both on and off LKML. A Documentation/ABI/testing/sysfs-gpio update is ready to submit once this merges to mainline. [akpm@linux-foundation.org: a few maintenance build fixes] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Cc: Guennadi Liakhovetski <g.liakhovetski@pengutronix.de> Cc: Greg KH <greg@kroah.com> Cc: Kay Sievers <kay.sievers@vrfy.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-07-25 01:46:07 -07:00
gpio: sysfs interface This adds a simple sysfs interface for GPIOs. /sys/class/gpio /export ... asks the kernel to export a GPIO to userspace /unexport ... to return a GPIO to the kernel /gpioN ... for each exported GPIO #N /value ... always readable, writes fail for input GPIOs /direction ... r/w as: in, out (default low); write high, low /gpiochipN ... for each gpiochip; #N is its first GPIO /base ... (r/o) same as N /label ... (r/o) descriptive, not necessarily unique /ngpio ... (r/o) number of GPIOs; numbered N .. N+(ngpio - 1) GPIOs claimed by kernel code may be exported by its owner using a new gpio_export() call, which should be most useful for driver debugging. Such exports may optionally be done without a "direction" attribute. Userspace may ask to take over a GPIO by writing to a sysfs control file, helping to cope with incomplete board support or other "one-off" requirements that don't merit full kernel support: echo 23 > /sys/class/gpio/export ... will gpio_request(23, "sysfs") and gpio_export(23); use /sys/class/gpio/gpio-23/direction to (re)configure it, when that GPIO can be used as both input and output. echo 23 > /sys/class/gpio/unexport ... will gpio_free(23), when it was exported as above The extra D-space footprint is a few hundred bytes, except for the sysfs resources associated with each exported GPIO. The additional I-space footprint is about two thirds of the current size of gpiolib (!). Since no /dev node creation is involved, no "udev" support is needed. Related changes: * This adds a device pointer to "struct gpio_chip". When GPIO providers initialize that, sysfs gpio class devices become children of that device instead of being "virtual" devices. * The (few) gpio_chip providers which have such a device node have been updated. * Some gpio_chip drivers also needed to update their module "owner" field ... for which missing kerneldoc was added. * Some gpio_chips don't support input GPIOs. Those GPIOs are now flagged appropriately when the chip is registered. Based on previous patches, and discussion both on and off LKML. A Documentation/ABI/testing/sysfs-gpio update is ready to submit once this merges to mainline. [akpm@linux-foundation.org: a few maintenance build fixes] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Cc: Guennadi Liakhovetski <g.liakhovetski@pengutronix.de> Cc: Greg KH <greg@kroah.com> Cc: Kay Sievers <kay.sievers@vrfy.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-07-25 01:46:07 -07:00
gpio: sysfs interface This adds a simple sysfs interface for GPIOs. /sys/class/gpio /export ... asks the kernel to export a GPIO to userspace /unexport ... to return a GPIO to the kernel /gpioN ... for each exported GPIO #N /value ... always readable, writes fail for input GPIOs /direction ... r/w as: in, out (default low); write high, low /gpiochipN ... for each gpiochip; #N is its first GPIO /base ... (r/o) same as N /label ... (r/o) descriptive, not necessarily unique /ngpio ... (r/o) number of GPIOs; numbered N .. N+(ngpio - 1) GPIOs claimed by kernel code may be exported by its owner using a new gpio_export() call, which should be most useful for driver debugging. Such exports may optionally be done without a "direction" attribute. Userspace may ask to take over a GPIO by writing to a sysfs control file, helping to cope with incomplete board support or other "one-off" requirements that don't merit full kernel support: echo 23 > /sys/class/gpio/export ... will gpio_request(23, "sysfs") and gpio_export(23); use /sys/class/gpio/gpio-23/direction to (re)configure it, when that GPIO can be used as both input and output. echo 23 > /sys/class/gpio/unexport ... will gpio_free(23), when it was exported as above The extra D-space footprint is a few hundred bytes, except for the sysfs resources associated with each exported GPIO. The additional I-space footprint is about two thirds of the current size of gpiolib (!). Since no /dev node creation is involved, no "udev" support is needed. Related changes: * This adds a device pointer to "struct gpio_chip". When GPIO providers initialize that, sysfs gpio class devices become children of that device instead of being "virtual" devices. * The (few) gpio_chip providers which have such a device node have been updated. * Some gpio_chip drivers also needed to update their module "owner" field ... for which missing kerneldoc was added. * Some gpio_chips don't support input GPIOs. Those GPIOs are now flagged appropriately when the chip is registered. Based on previous patches, and discussion both on and off LKML. A Documentation/ABI/testing/sysfs-gpio update is ready to submit once this merges to mainline. [akpm@linux-foundation.org: a few maintenance build fixes] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Cc: Guennadi Liakhovetski <g.liakhovetski@pengutronix.de> Cc: Greg KH <greg@kroah.com> Cc: Kay Sievers <kay.sievers@vrfy.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-07-25 01:46:07 -07:00
gpio: idio-16: Migrate to the regmap API The regmap API supports IO port accessors so we can take advantage of regmap abstractions rather than handling access to the device registers directly in the driver. By leveraging the regmap API, the idio-16 library is reduced to simply a devm_idio_16_regmap_register() function and a configuration structure struct idio_16_regmap_config. Legacy functions and code will be removed once all consumers have migrated to the new idio-16 library interface. For IDIO-16 devices we have the following IRQ registers: Base Address +1 (Write): Clear Interrupt Base Address +2 (Read): Enable Interrupt Base Address +2 (Write): Disable Interrupt An interrupt is asserted whenever a change-of-state is detected on any of the inputs. Any write to 0x2 will disable interrupts, while any read will enable interrupts. Interrupts are cleared by a write to 0x1. For 104-IDIO-16 devices, there is no IRQ status register, so software has to assume that if an interrupt is raised then it was for the 104-IDIO-16 device. For PCI-IDIO-16 devices, there is an additional IRQ register: Base Address +6 (Read): Interrupt Status Interrupt status can be read from 0x6 where bit 2 set indicates that an IRQ has been generated. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/b45081958ab53dfa697f4a8b15f1bfba46718068.1680618405.git.william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2023-08-10 18:00:38 -04:00
gpio: raspberrypi-ext: fix firmware dependency When the firmware driver is a loadable module, the gpio driver cannot be built-in: drivers/gpio/gpio-raspberrypi-exp.o: In function `rpi_exp_gpio_set': gpio-raspberrypi-exp.c:(.text+0xb4): undefined reference to `rpi_firmware_property' drivers/gpio/gpio-raspberrypi-exp.o: In function `rpi_exp_gpio_get': gpio-raspberrypi-exp.c:(.text+0x1ec): undefined reference to `rpi_firmware_property' drivers/gpio/gpio-raspberrypi-exp.o: In function `rpi_exp_gpio_get_direction': gpio-raspberrypi-exp.c:(.text+0x360): undefined reference to `rpi_firmware_property' drivers/gpio/gpio-raspberrypi-exp.o: In function `rpi_exp_gpio_get_polarity': gpio-raspberrypi-exp.c:(.text+0x4d4): undefined reference to `rpi_firmware_property' drivers/gpio/gpio-raspberrypi-exp.o: In function `rpi_exp_gpio_dir_out': gpio-raspberrypi-exp.c:(.text+0x670): undefined reference to `rpi_firmware_property' drivers/gpio/gpio-raspberrypi-exp.o:gpio-raspberrypi-exp.c:(.text+0x7fc): more undefined references to `rpi_firmware_property' follow drivers/gpio/gpio-raspberrypi-exp.o: In function `rpi_exp_gpio_dir_in': drivers/gpio/gpio-raspberrypi-exp.o: In function `rpi_exp_gpio_probe': gpio-raspberrypi-exp.c:(.text+0x93c): undefined reference to `rpi_firmware_get' We already have a Kconfig dependency for it, but when compile-testing, it is disregarded. This changes the dependency so that compile-testing is only done when the firmware driver is completely disabled. Fixes: a98d90e7d588 ("gpio: raspberrypi-exp: Driver for RPi3 GPIO expander via mailbox service") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-28 14:48:08 +01:00
gpio: add a driver for the Synopsys DesignWare APB GPIO block The Synopsys DesignWare block is used in some ARM devices (picoxcell) and can be configured to provide multiple banks of GPIO pins. v12: - Add irq_startup/shutdown - do irq_create_mapping() in probe, irq_find_mapping() in to_irq() - Adjust mappings to show support for 1 gpio per port. - gpio-cells = <1> v11: - Use NULL when checking existence of 'interrupts' property - Bindings descriptions cleanup v10: - in documentation nr-gpio -> nr-gpios v9: - cleanup in dt bindings doc - use of_get_child_count() v8: - remove socfpga.dtsi changes - minor cleanup in devicetree documentation v7: - use irq_generic_chip - support one irq per gpio line or one irq for many - s/bank/port/ and other cleanup v6: - (atull) squash the set of patches - use linear irq domain - build fixes. Original driver was reviewed on v3.2. - Fix setting irq edge type for 'rising' and 'both'. - Support as a loadable module. - Use bgpio_chip's spinlock during register access. - Clean up register names to match spec - s/bank/port/ because register names use the word 'port' - s/nr-gpio/nr-gpios/ - don't get/put the of_node - remove signoffs/acked-by's because of changes - other cleanup v5: - handle sparse bank population correctly v3: - depend on rather than select IRQ_DOMAIN - split IRQ support into a separate patch v2: - use Rob Herring's irqdomain in generic irq chip patches - use reg property to indicate bank index - support irqs on both edges based on LinusW's u300 driver Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Alan Tull <atull@altera.com> Reviewed-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 17:01:01 -06:00
gpio: dwapb: Convert driver to using the GPIO-lib-based IRQ-chip GPIO-lib provides a ready-to-use interface to initialize an IRQ-chip on top of a GPIO chip. It's better from maintainability and readability point of view to use one instead of supporting a hand-written Generic IRQ-chip-based implementation. Moreover the new implementation won't cause much functional overhead but will provide a cleaner driver code. All of that makes the DW APB GPIO driver conversion pretty much justified especially seeing a tendency of the other GPIO drivers getting converted too. Here is what we do in the framework of this commit to convert the driver to using the GPIO-lib-based IRQ-chip interface: 1) IRQ ack, mask and unmask callbacks are locally defined instead of using the Generic IRQ-chip ones. 2) An irq_chip structure instance is embedded into the dwapb_gpio private data. Note we can't have a static instance of that structure since GPIO-lib will add some hooks into it by calling gpiochip_set_irq_hooks(). A warning about that would have been printed by the GPIO-lib code if we used a single irq_chip structure instance for multiple DW APB GPIO controllers. 3) Initialize the gpio_irq_chip structure embedded into the gpio_chip descriptor. By default there is no IRQ enabled so any event raised will be handled by the handle_bad_irq() IRQ flow handler. If DW APB GPIO IP-core is synthesized to have non-shared reference IRQ-lines, then as before the hierarchical and cascaded cases are distinguished by checking how many parental IRQs are defined. (Note irq_set_chained_handler_and_data() won't initialize IRQs, which descriptors couldn't be found.) If DW APB GPIO IP is used on a platform with shared IRQ line, then we simply won't let the GPIO-lib to initialize the parental IRQs, but will handle them locally in the driver. 4) Discard linear IRQ-domain and Generic IRQ-chip initialization, since GPIO-lib IRQ-chip interface will create a new domain and accept a standard IRQ-chip structure pointer based on the setting we provided in the gpio_irq_chip structure. 5) Manually select a proper IRQ flow handler directly in the irq_set_type() callback by calling irq_set_handler_locked() method, since an ordinary (not Generic) irq_chip descriptor is now utilized. Note this shalln't give any regression 6) Alter CONFIG_GPIO_DWAPB kernel config to select CONFIG_GPIOLIB_IRQCHIP instead of CONFIG_GENERIC_IRQ_CHIP. Note neither 4) nor 5) shall cause a regression of commit 6a2f4b7dadd5 ("gpio: dwapb: use a second irq chip"), since the later isn't properly used here anyway. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20200730152808.2955-6-Sergey.Semin@baikalelectronics.ru Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-30 18:28:02 +03:00
gpio: add a driver for the Synopsys DesignWare APB GPIO block The Synopsys DesignWare block is used in some ARM devices (picoxcell) and can be configured to provide multiple banks of GPIO pins. v12: - Add irq_startup/shutdown - do irq_create_mapping() in probe, irq_find_mapping() in to_irq() - Adjust mappings to show support for 1 gpio per port. - gpio-cells = <1> v11: - Use NULL when checking existence of 'interrupts' property - Bindings descriptions cleanup v10: - in documentation nr-gpio -> nr-gpios v9: - cleanup in dt bindings doc - use of_get_child_count() v8: - remove socfpga.dtsi changes - minor cleanup in devicetree documentation v7: - use irq_generic_chip - support one irq per gpio line or one irq for many - s/bank/port/ and other cleanup v6: - (atull) squash the set of patches - use linear irq domain - build fixes. Original driver was reviewed on v3.2. - Fix setting irq edge type for 'rising' and 'both'. - Support as a loadable module. - Use bgpio_chip's spinlock during register access. - Clean up register names to match spec - s/bank/port/ because register names use the word 'port' - s/nr-gpio/nr-gpios/ - don't get/put the of_node - remove signoffs/acked-by's because of changes - other cleanup v5: - handle sparse bank population correctly v3: - depend on rather than select IRQ_DOMAIN - split IRQ support into a separate patch v2: - use Rob Herring's irqdomain in generic irq chip patches - use reg property to indicate bank index - support irqs on both edges based on LinusW's u300 driver Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Alan Tull <atull@altera.com> Reviewed-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25 17:01:01 -06:00
gpio: Add GPIO driver for Nintendo Wii The Nintendo Wii's chipset (called "Hollywood") has a GPIO controller that supports a configurable number of pins (up to 32), interrupts, and some special mechanisms to share the controller between the system's security processor (an ARM926) and the PowerPC CPU. Pin multiplexing is not supported. This patch adds a basic driver for this GPIO controller. Interrupt support will come in a later patch. This patch is based on code developed by Albert Herranz and the GameCube Linux Team, file arch/powerpc/platforms/embedded6xx/hlwd-gpio.c, available at https://github.com/DeltaResero/GC-Wii-Linux-Kernels, but has grown quite dissimilar. v3: - Do some style cleanups, as suggest by Andy Shevchenko v2: - Change hlwd_gpio_driver.driver.name to "gpio-hlwd" to match the filename (was "hlwd_gpio") - Remove unnecessary include of linux/of_gpio.h, as suggested by Linus Walleij. - Add struct device pointer to context struct to make it possible to use dev_info(hlwd->dev, "..."), as suggested by Linus Walleij - Use the GPIO_GENERIC library to reduce code size, as suggested by Linus Walleij - Use iowrite32be instead of __raw_writel for big-endian MMIO access, as suggested by Linus Walleij - Remove commit message paragraph suggesting to diff against the original driver, because it's so different now Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Cc: Albert Herranz <albert_herranz@yahoo.es> Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-09 13:07:29 +01:00
gpio: Add GPIO driver for Nintendo Wii The Nintendo Wii's chipset (called "Hollywood") has a GPIO controller that supports a configurable number of pins (up to 32), interrupts, and some special mechanisms to share the controller between the system's security processor (an ARM926) and the PowerPC CPU. Pin multiplexing is not supported. This patch adds a basic driver for this GPIO controller. Interrupt support will come in a later patch. This patch is based on code developed by Albert Herranz and the GameCube Linux Team, file arch/powerpc/platforms/embedded6xx/hlwd-gpio.c, available at https://github.com/DeltaResero/GC-Wii-Linux-Kernels, but has grown quite dissimilar. v3: - Do some style cleanups, as suggest by Andy Shevchenko v2: - Change hlwd_gpio_driver.driver.name to "gpio-hlwd" to match the filename (was "hlwd_gpio") - Remove unnecessary include of linux/of_gpio.h, as suggested by Linus Walleij. - Add struct device pointer to context struct to make it possible to use dev_info(hlwd->dev, "..."), as suggested by Linus Walleij - Use the GPIO_GENERIC library to reduce code size, as suggested by Linus Walleij - Use iowrite32be instead of __raw_writel for big-endian MMIO access, as suggested by Linus Walleij - Remove commit message paragraph suggesting to diff against the original driver, because it's so different now Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Cc: Albert Herranz <albert_herranz@yahoo.es> Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-09 13:07:29 +01:00
gpio: lpc18xx: add GPIO pin interrupt controller support The change adds support of LPC18xx/LPC43xx GPIO pin interrupt controller block within SoC GPIO controller. The new interrupt controller driver allows to configure and capture edge or level interrupts on 8 arbitrary selectedinput GPIO pins, and lift the signals to be reported as NVIC rising edge interrupts. Configuration of a particular GPIO pin to serve as interrupt and its mapping to an interrupt on NVIC is done by SCU pin controller, for more details see description of 'nxp,gpio-pin-interrupt' device tree property of a GPIO pin [1]. From LPC18xx and LPC43xx User Manuals the GPIO controller consists of the following blocks: * GPIO pin interrupt block at 0x40087000, this change adds its support, * GPIO GROUP0 interrupt block at 0x40088000, * GPIO GROUP1 interrupt block at 0x40089000, * GPIO port block at 0x400F4000, it is supported by the original driver. While all 4 sub-controller blocks have their own I/O addresses, moreover all 3 interrupt blocks are APB0 peripherals and high-speed GPIO block is an AHB slave, according to the hardware manual the GPIO controller is seen as a single block, and 4 sub-controllers have the shared reset signal RGU #28 and clock to register interface CLK_CPU_GPIO on CCU1. Likely support of two GPIO group interrupt blocks won't be added in short term, because the mechanism to mask several interrupt sources is not well defined. [1] Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-11-29 00:48:41 +02:00
gpio: ws16c48: Migrate to the regmap API The regmap API supports IO port accessors so we can take advantage of regmap abstractions rather than handling access to the device registers directly in the driver. The WinSystems WS16C48 provides the following registers: Offset 0x0-0x5: Port 0-5 I/O Offset 0x6: Int_Pending Offset 0x7: Page/Lock Offset 0x8-0xA (Page 1): Pol_0-Pol_2 Offset 0x8-0xA (Page 2): Enab_0-Enab_2 Offset 0x8-0xA (Page 3): Int_ID0-Int_ID2 Port 0-5 I/O provides access to 48 lines of digital I/O across six registers, each bit position corresponding to the respective line. Writing a 1 to a respective bit position causes that output pin to sink current, while writing a 0 to the same bit position causes that output pin to go to a high-impedance state and allows it to be used an input. Reads on a port report the inverted state (0 = high, 1 = low) of an I/O pin when used in input mode. Interrupts are supported on Port 0-2. Int_Pending is a read-only register that reports the combined state of the INT_ID0 through INT_ID2 registers; an interrupt pending is indicated when any of the low three bits are set. The Page/Lock register provides the following bits: Bit 0-5: Port 0-5 I/O Lock Bit 6-7: Page 0-3 Selection For Bits 0-5, writing a 1 to a respective bit position locks the output state of the corresponding I/O port. Writing the page number to Bits 6-7 selects that respective register page for use. Pol_0-Pol_2 are accessible when Page 1 is selected. Writing a 1 to a respective bit position selects the rising edge detection interrupts for that input line, while writing a 0 to the same bit position selects the falling edge detection interrupts. Enab_0-Enab_2 are accessible when Page 2 is selected. Writing a 1 to a respective bit position enables interrupts for that input line, while writing a 0 to that same bit position clears and disables interrupts for that input line. Int_ID0-Int_ID2 are accessible when Page 3 is selected. A respective bit when read as a 1 indicates that an edge of the polarity set in the corresponding polarity register was detected for the corresponding input line. Writing any value to this register clears all pending interrupts for the register. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/f59de81e80f7198bcfa9a15615c459c38b5d0e08.1680708357.git.william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2023-08-10 18:00:43 -04:00
gpio: ws16c48: Migrate to the regmap API The regmap API supports IO port accessors so we can take advantage of regmap abstractions rather than handling access to the device registers directly in the driver. The WinSystems WS16C48 provides the following registers: Offset 0x0-0x5: Port 0-5 I/O Offset 0x6: Int_Pending Offset 0x7: Page/Lock Offset 0x8-0xA (Page 1): Pol_0-Pol_2 Offset 0x8-0xA (Page 2): Enab_0-Enab_2 Offset 0x8-0xA (Page 3): Int_ID0-Int_ID2 Port 0-5 I/O provides access to 48 lines of digital I/O across six registers, each bit position corresponding to the respective line. Writing a 1 to a respective bit position causes that output pin to sink current, while writing a 0 to the same bit position causes that output pin to go to a high-impedance state and allows it to be used an input. Reads on a port report the inverted state (0 = high, 1 = low) of an I/O pin when used in input mode. Interrupts are supported on Port 0-2. Int_Pending is a read-only register that reports the combined state of the INT_ID0 through INT_ID2 registers; an interrupt pending is indicated when any of the low three bits are set. The Page/Lock register provides the following bits: Bit 0-5: Port 0-5 I/O Lock Bit 6-7: Page 0-3 Selection For Bits 0-5, writing a 1 to a respective bit position locks the output state of the corresponding I/O port. Writing the page number to Bits 6-7 selects that respective register page for use. Pol_0-Pol_2 are accessible when Page 1 is selected. Writing a 1 to a respective bit position selects the rising edge detection interrupts for that input line, while writing a 0 to the same bit position selects the falling edge detection interrupts. Enab_0-Enab_2 are accessible when Page 2 is selected. Writing a 1 to a respective bit position enables interrupts for that input line, while writing a 0 to that same bit position clears and disables interrupts for that input line. Int_ID0-Int_ID2 are accessible when Page 3 is selected. A respective bit when read as a 1 indicates that an edge of the polarity set in the corresponding polarity register was detected for the corresponding input line. Writing any value to this register clears all pending interrupts for the register. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/f59de81e80f7198bcfa9a15615c459c38b5d0e08.1680708357.git.william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2023-08-10 18:00:43 -04:00
gpio: Add Intel WhiskeyCove PMIC GPIO driver This patch introduces a separate GPIO driver for Intel WhiskeyCove PMIC. This driver is based on gpio-crystalcove.c. Changes in v7: - Fixed various coding style comments from Andy Shevchenko Changes in v6: - Removed unnecessary wcove_gpio_remove() - Used devm_gpiochip_remove() instead of gpiochip_remove() - Various coding style changes per Mika's comment Changes in v5: - Revisited the interrupt handler code to iterate until all pending interrupts are handled. This change is to avoid missing interrupt when we're inside the interrupt handler. - Used regmap_bulk_read() to read address adjacent registers. Changes in v4: - Converted CTLI_INTCNT_XX macros to less verbose ones INT_DETECT_XX. - Add comments about why there is no .pm for the driver. - Header files re-ordered. - Various coding style change to address Andy's comments. Changes in v3: - Fixed the year in copyright line(2015-->2016). - Removed DRV_NAME macro. - Added kernel-doc for regmap_irq_chip of the wcove_gpio structure. - Line length fix. Changes in v2: - Typo fix (Whsikey --> Whiskey). - Included linux/gpio/driver.h instead of linux/gpio.h - Implemented .set_single_ended(). - Added GPIO register description. - Replaced container_of() with gpiochip_get_data(). - Removed unnecessary "if (gpio > WCOVE_VGPIO_NUM" check. - Removed the device id table and added MODULE_ALIAS(). Signed-off-by: Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com> Signed-off-by: Bin Gao <bin.gao@intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-07-25 14:59:38 -07:00
gpio: Add Intel WhiskeyCove PMIC GPIO driver This patch introduces a separate GPIO driver for Intel WhiskeyCove PMIC. This driver is based on gpio-crystalcove.c. Changes in v7: - Fixed various coding style comments from Andy Shevchenko Changes in v6: - Removed unnecessary wcove_gpio_remove() - Used devm_gpiochip_remove() instead of gpiochip_remove() - Various coding style changes per Mika's comment Changes in v5: - Revisited the interrupt handler code to iterate until all pending interrupts are handled. This change is to avoid missing interrupt when we're inside the interrupt handler. - Used regmap_bulk_read() to read address adjacent registers. Changes in v4: - Converted CTLI_INTCNT_XX macros to less verbose ones INT_DETECT_XX. - Add comments about why there is no .pm for the driver. - Header files re-ordered. - Various coding style change to address Andy's comments. Changes in v3: - Fixed the year in copyright line(2015-->2016). - Removed DRV_NAME macro. - Added kernel-doc for regmap_irq_chip of the wcove_gpio structure. - Line length fix. Changes in v2: - Typo fix (Whsikey --> Whiskey). - Included linux/gpio/driver.h instead of linux/gpio.h - Implemented .set_single_ended(). - Added GPIO register description. - Replaced container_of() with gpiochip_get_data(). - Removed unnecessary "if (gpio > WCOVE_VGPIO_NUM" check. - Removed the device id table and added MODULE_ALIAS(). Signed-off-by: Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com> Signed-off-by: Bin Gao <bin.gao@intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-07-25 14:59:38 -07:00
gpio: Add Intel WhiskeyCove PMIC GPIO driver This patch introduces a separate GPIO driver for Intel WhiskeyCove PMIC. This driver is based on gpio-crystalcove.c. Changes in v7: - Fixed various coding style comments from Andy Shevchenko Changes in v6: - Removed unnecessary wcove_gpio_remove() - Used devm_gpiochip_remove() instead of gpiochip_remove() - Various coding style changes per Mika's comment Changes in v5: - Revisited the interrupt handler code to iterate until all pending interrupts are handled. This change is to avoid missing interrupt when we're inside the interrupt handler. - Used regmap_bulk_read() to read address adjacent registers. Changes in v4: - Converted CTLI_INTCNT_XX macros to less verbose ones INT_DETECT_XX. - Add comments about why there is no .pm for the driver. - Header files re-ordered. - Various coding style change to address Andy's comments. Changes in v3: - Fixed the year in copyright line(2015-->2016). - Removed DRV_NAME macro. - Added kernel-doc for regmap_irq_chip of the wcove_gpio structure. - Line length fix. Changes in v2: - Typo fix (Whsikey --> Whiskey). - Included linux/gpio/driver.h instead of linux/gpio.h - Implemented .set_single_ended(). - Added GPIO register description. - Replaced container_of() with gpiochip_get_data(). - Removed unnecessary "if (gpio > WCOVE_VGPIO_NUM" check. - Removed the device id table and added MODULE_ALIAS(). Signed-off-by: Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com> Signed-off-by: Bin Gao <bin.gao@intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-07-25 14:59:38 -07:00
gpio: pcie-idio-24: Migrate to the regmap API The regmap API supports IO port accessors so we can take advantage of regmap abstractions rather than handling access to the device registers directly in the driver. For the PCIe-IDIO-24 series of devices, the following BARs are available: BAR[0]: memory mapped PEX8311 BAR[1]: I/O mapped PEX8311 BAR[2]: I/O mapped card registers There are 24 FET Output lines, 24 Isolated Input lines, and 8 TTL/CMOS lines (which may be configured for either output or input). The GPIO lines are exposed by the following card registers: Base +0x0-0x2 (Read/Write): FET Outputs Base +0xB (Read/Write): TTL/CMOS Base +0x4-0x6 (Read): Isolated Inputs Base +0x7 (Read): TTL/CMOS In order for the device to support interrupts, the PLX PEX8311 internal PCI wire interrupt and local interrupt input must first be enabled. The following card registers for Change-Of-State may be used: Base +0x8-0xA (Read): COS Status Inputs Base +0x8-0xA (Write): COS Clear Inputs Base +0xB (Read): COS Status TTL/CMOS Base +0xB (Write): COS Clear TTL/CMOS Base +0xE (Read/Write): COS Enable The COS Enable register is used to enable/disable interrupts and configure the interrupt levels; each bit maps to a group of eight inputs as described below: Bit 0: IRQ EN Rising Edge IN0-7 Bit 1: IRQ EN Rising Edge IN8-15 Bit 2: IRQ EN Rising Edge IN16-23 Bit 3: IRQ EN Rising Edge TTL0-7 Bit 4: IRQ EN Falling Edge IN0-7 Bit 5: IRQ EN Falling Edge IN8-15 Bit 6: IRQ EN Falling Edge IN16-23 Bit 7: IRQ EN Falling Edge TTL0-7 An interrupt is asserted when a change-of-state matching the interrupt level configuration respective for a particular group of eight inputs with enabled COS is detected. The COS Status registers may be read to determine which inputs have changed; if interrupts were enabled, an IRQ will be generated for the set bits in these registers. Writing the value read from the COS Status register back to the respective COS Clear register will clear just those interrupts. Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/3091e387b1d2eac011a1d84e493663aa2acf982e.1680708357.git.william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2023-08-10 18:00:42 -04:00
gpio: pcie-idio-24: Migrate to the regmap API The regmap API supports IO port accessors so we can take advantage of regmap abstractions rather than handling access to the device registers directly in the driver. For the PCIe-IDIO-24 series of devices, the following BARs are available: BAR[0]: memory mapped PEX8311 BAR[1]: I/O mapped PEX8311 BAR[2]: I/O mapped card registers There are 24 FET Output lines, 24 Isolated Input lines, and 8 TTL/CMOS lines (which may be configured for either output or input). The GPIO lines are exposed by the following card registers: Base +0x0-0x2 (Read/Write): FET Outputs Base +0xB (Read/Write): TTL/CMOS Base +0x4-0x6 (Read): Isolated Inputs Base +0x7 (Read): TTL/CMOS In order for the device to support interrupts, the PLX PEX8311 internal PCI wire interrupt and local interrupt input must first be enabled. The following card registers for Change-Of-State may be used: Base +0x8-0xA (Read): COS Status Inputs Base +0x8-0xA (Write): COS Clear Inputs Base +0xB (Read): COS Status TTL/CMOS Base +0xB (Write): COS Clear TTL/CMOS Base +0xE (Read/Write): COS Enable The COS Enable register is used to enable/disable interrupts and configure the interrupt levels; each bit maps to a group of eight inputs as described below: Bit 0: IRQ EN Rising Edge IN0-7 Bit 1: IRQ EN Rising Edge IN8-15 Bit 2: IRQ EN Rising Edge IN16-23 Bit 3: IRQ EN Rising Edge TTL0-7 Bit 4: IRQ EN Falling Edge IN0-7 Bit 5: IRQ EN Falling Edge IN8-15 Bit 6: IRQ EN Falling Edge IN16-23 Bit 7: IRQ EN Falling Edge TTL0-7 An interrupt is asserted when a change-of-state matching the interrupt level configuration respective for a particular group of eight inputs with enabled COS is detected. The COS Status registers may be read to determine which inputs have changed; if interrupts were enabled, an IRQ will be generated for the set bits in these registers. Writing the value read from the COS Status register back to the respective COS Clear register will clear just those interrupts. Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/3091e387b1d2eac011a1d84e493663aa2acf982e.1680708357.git.william.gray@linaro.org/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2023-08-10 18:00:42 -04:00