kernel/linux
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ synced 2026-11-13 07:31:07 +00:00
Code Issues Releases Packages Activity
linux/drivers/phy/tegra/xusb.h

517 lines
12 KiB
Raw Normal View History

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 263 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141901.208660670@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-29 07:18:02 -07:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: add utmi pad power on/down ops Add utmi_pad_power_on/down ops for each SOC instead of exporting tegra_phy_xusb_utmi_pad_power_on/down directly for Tegra186 chip. Signed-off-by: BH Hsieh <bhsieh@nvidia.com> Signed-off-by: Jim Lin <jilin@nvidia.com> Link: https://lore.kernel.org/r/20220816082353.13390-2-jilin@nvidia.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-08-16 16:23:52 +08:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add Tegra234 support Add support for the XUSB pad controller found on Tegra234 SoCs. It is mostly similar to the same IP found on Tegra194, because most of the Tegra234 XUSB PADCTL registers definition and programming sequence are the same as Tegra194, Tegra234 XUSB PADCTL can share the same driver with Tegra186 and Tegra194 XUSB PADCTL. Introduce a new feature, USB2 HW tracking, for Tegra234. The feature is to enable HW periodical PAD tracking which measure and capture the electric parameters of USB2.0 PAD. Signed-off-by: Sing-Han Chen <singhanc@nvidia.com> Co-developed-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230111110450.24617-6-jonathanh@nvidia.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-01-11 11:04:49 +00:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add sleepwalk and suspend/resume This commit adds sleepwalk/wake and suspend/resume interfaces to Tegra XUSB PHY driver. Tegra XUSB host controller driver makes use of sleepwalk functions to enable/disable sleepwalk circuit which is in always-on partition and can respond to USB resume signals when controller is not powered. Sleepwalk can be enabled/disabled for any USB UPHY individually. - tegra_xusb_padctl_enable_phy_sleepwalk() - tegra_xusb_padctl_disable_phy_sleepwalk() Tegra XUSB host controller driver makes use of wake functions to enable/disable/query wake circuit which is in always-on partition can wake system up when USB resume happens. Wake circuit can be enabled/disabled for any USB PHY individually. - tegra_xusb_padctl_enable_phy_wake() - tegra_xusb_padctl_disable_phy_wake() - tegra_xusb_padctl_remote_wake_detected() This commit also adds two system suspend stubs that can be used to save and restore XUSB PADCTL context during system suspend and resume. - tegra_xusb_padctl_suspend_noirq() - tegra_xusb_padctl_resume_noirq() Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-By: Vinod Koul <vkoul@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-20 15:34:06 +08:00
phy: tegra: xusb: Parse dual-role mode property The device tree bindings document the "mode" property of "ports" subnodes, but the driver was not parsing the property. In preparation for adding role switching, parse the property at probe time. Based on work by JC Kuo <jckuo@nvidia.com>. Reviewed-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-02-21 16:46:32 +01:00
phy: tegra: xusb: Add usb-role-switch support If usb-role-switch property is present in USB 2 port, register usb-role-switch to receive usb role changes. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> [treding@nvidia.com: rebase onto Greg's usb-next branch] Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-02-10 13:41:29 +05:30
phy: tegra: xusb: Parse dual-role mode property The device tree bindings document the "mode" property of "ports" subnodes, but the driver was not parsing the property. In preparation for adding role switching, parse the property at probe time. Based on work by JC Kuo <jckuo@nvidia.com>. Reviewed-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-02-21 16:46:32 +01:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add Tegra210 lane_iddq operation As per Tegra210 TRM, before changing lane assignments, driver should keep lanes in IDDQ and sleep state; after changing lane assignments, driver should bring lanes out of IDDQ. This commit implements the required operations. Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-By: Vinod Koul <vkoul@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-20 15:34:05 +08:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add Tegra186 support Add support for the XUSB pad controller found on Tegra186 SoCs. It is mostly similar to the same IP found on earlier chips, but the number of pads exposed differs, as do the programming sequences. Note that the DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL power supplies of the XUSB pad controller require strict power sequencing and are therefore controlled by the PMIC on Tegra186. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> [dan.carpenter@oracle.com: Fix testing the wrong variable in probe()] Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> [yuehaibing@huawei.com: Make two functions static to fix sparse warning] Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-02-21 16:46:34 +01:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add Tegra186 support Add support for the XUSB pad controller found on Tegra186 SoCs. It is mostly similar to the same IP found on earlier chips, but the number of pads exposed differs, as do the programming sequences. Note that the DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL power supplies of the XUSB pad controller require strict power sequencing and are therefore controlled by the PMIC on Tegra186. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> [dan.carpenter@oracle.com: Fix testing the wrong variable in probe()] Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> [yuehaibing@huawei.com: Make two functions static to fix sparse warning] Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-02-21 16:46:34 +01:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add Tegra210 lane_iddq operation As per Tegra210 TRM, before changing lane assignments, driver should keep lanes in IDDQ and sleep state; after changing lane assignments, driver should bring lanes out of IDDQ. This commit implements the required operations. Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-By: Vinod Koul <vkoul@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-20 15:34:05 +08:00
phy: tegra: xusb: Add sleepwalk and suspend/resume This commit adds sleepwalk/wake and suspend/resume interfaces to Tegra XUSB PHY driver. Tegra XUSB host controller driver makes use of sleepwalk functions to enable/disable sleepwalk circuit which is in always-on partition and can respond to USB resume signals when controller is not powered. Sleepwalk can be enabled/disabled for any USB UPHY individually. - tegra_xusb_padctl_enable_phy_sleepwalk() - tegra_xusb_padctl_disable_phy_sleepwalk() Tegra XUSB host controller driver makes use of wake functions to enable/disable/query wake circuit which is in always-on partition can wake system up when USB resume happens. Wake circuit can be enabled/disabled for any USB PHY individually. - tegra_xusb_padctl_enable_phy_wake() - tegra_xusb_padctl_disable_phy_wake() - tegra_xusb_padctl_remote_wake_detected() This commit also adds two system suspend stubs that can be used to save and restore XUSB PADCTL context during system suspend and resume. - tegra_xusb_padctl_suspend_noirq() - tegra_xusb_padctl_resume_noirq() Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-By: Vinod Koul <vkoul@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-20 15:34:06 +08:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Move usb3 port init for Tegra210 The programming sequence in tegra210_usb3_port_enable() is required for both cold boot and SC7 exit, and must be performed only after PEX/SATA UPHY is initialized. Therefore, this commit moves the programming sequence to tegra210_usb3_phy_power_on(). PCIE/SATA phy .power_on() stub will invoke tegra210_usb3_phy_power_on() if the lane is assigned for XUSB super-speed. Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-By: Vinod Koul <vkoul@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-20 15:34:03 +08:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add Tegra186 support Add support for the XUSB pad controller found on Tegra186 SoCs. It is mostly similar to the same IP found on earlier chips, but the number of pads exposed differs, as do the programming sequences. Note that the DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL power supplies of the XUSB pad controller require strict power sequencing and are therefore controlled by the PMIC on Tegra186. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> [dan.carpenter@oracle.com: Fix testing the wrong variable in probe()] Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> [yuehaibing@huawei.com: Make two functions static to fix sparse warning] Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-02-21 16:46:34 +01:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Rearrange UPHY init on Tegra210 This commit is a preparation for enabling XUSB SC7 support. It rearranges Tegra210 XUSB PADCTL UPHY initialization sequence, for the following reasons: 1. PLLE hardware power sequencer has to be enabled only after both PEX UPHY PLL and SATA UPHY PLL are initialized. tegra210_uphy_init() -> tegra210_pex_uphy_enable() -> tegra210_sata_uphy_enable() -> tegra210_plle_hw_sequence_start() -> tegra210_aux_mux_lp0_clamp_disable() 2. At cold boot and SC7 exit, the following bits must be cleared after PEX/SATA lanes are out of IDDQ (IDDQ_DISABLE=1). a. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN, b. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY c. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN tegra210_pex_uphy_enable() and tegra210_sata_uphy_enable() are in charge of bringing lanes out of IDDQ, and then AUX_MUX_LP0_* bits will be cleared by tegra210_aux_mux_lp0_clamp_disable(). 3. Once UPHY PLL hardware power sequencer is enabled, do not assert reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken. Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-By: Vinod Koul <vkoul@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-20 15:34:04 +08:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Rearrange UPHY init on Tegra210 This commit is a preparation for enabling XUSB SC7 support. It rearranges Tegra210 XUSB PADCTL UPHY initialization sequence, for the following reasons: 1. PLLE hardware power sequencer has to be enabled only after both PEX UPHY PLL and SATA UPHY PLL are initialized. tegra210_uphy_init() -> tegra210_pex_uphy_enable() -> tegra210_sata_uphy_enable() -> tegra210_plle_hw_sequence_start() -> tegra210_aux_mux_lp0_clamp_disable() 2. At cold boot and SC7 exit, the following bits must be cleared after PEX/SATA lanes are out of IDDQ (IDDQ_DISABLE=1). a. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN, b. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY c. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN tegra210_pex_uphy_enable() and tegra210_sata_uphy_enable() are in charge of bringing lanes out of IDDQ, and then AUX_MUX_LP0_* bits will be cleared by tegra210_aux_mux_lp0_clamp_disable(). 3. Once UPHY PLL hardware power sequencer is enabled, do not assert reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken. Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-By: Vinod Koul <vkoul@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-20 15:34:04 +08:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add usb-role-switch support If usb-role-switch property is present in USB 2 port, register usb-role-switch to receive usb role changes. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> [treding@nvidia.com: rebase onto Greg's usb-next branch] Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-02-10 13:41:29 +05:30
phy: tegra: xusb: Add usb-phy support For USB 2 ports that has usb-role-switch enabled, add usb-phy for corresponding USB 2 phy. USB role changes from role switch are then updated to corresponding host and device mode drivers via usb-phy notifier block. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> [treding@nvidia.com: rebase onto Greg's usb-next branch] Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-02-10 13:41:30 +05:30
phy: tegra: xusb: Add usb-role-switch support If usb-role-switch property is present in USB 2 port, register usb-role-switch to receive usb role changes. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> [treding@nvidia.com: rebase onto Greg's usb-next branch] Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-02-10 13:41:29 +05:30
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: Don't use device-managed API to allocate ports The device-managed allocation API doesn't work well with the life-cycle of device objects. Since ports have device objects allocated within, it can lead to situations where these devices need to stay around until after their parent pad controller has been unbound from its driver. The device-managed memory allocated for the port objects will, however, get freed when the pad controller unbinds from the driver. This can cause use-after-free errors down the road. Note that the device is deleted as part of the driver unbind operation, so there isn't much that can be done with it after that point, but the memory still needs to stay around to ensure none of the references are invalidated. One situation where this arises is when a VBUS supply is associated with a USB 2 or 3 port. When that supply is released using regulator_put() an SRCU call will queue the release of the device link connecting the port and the regulator after a grace period. This means that the regulator is going to keep on to the last reference of the port device even after the pad controller driver was unbound (which is when the memory backing the port device is freed). Fix this by allocating port objects using non-device-managed memory. Add release callbacks for these objects so that their memory gets freed when the last reference goes away. This decouples the port devices' lifetime from the "active" lifetime of the pad controller (i.e. the time during which the pad controller driver owns the device). Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-19 11:52:13 +01:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Parse dual-role mode property The device tree bindings document the "mode" property of "ports" subnodes, but the driver was not parsing the property. In preparation for adding role switching, parse the property at probe time. Based on work by JC Kuo <jckuo@nvidia.com>. Reviewed-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-02-21 16:46:32 +01:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add usb3 port fake support on Tegra210 On Tegra210, usb2 only otg/peripheral ports dont work in device mode. They need an assosciated usb3 port to work in device mode. Identify an unused usb3 port and assign it as a fake USB3 port to USB2 only port whose mode is otg/peripheral. Based on work by BH Hsieh <bhsieh@nvidia.com>. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-10-18 15:08:07 +05:30
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: Don't use device-managed API to allocate ports The device-managed allocation API doesn't work well with the life-cycle of device objects. Since ports have device objects allocated within, it can lead to situations where these devices need to stay around until after their parent pad controller has been unbound from its driver. The device-managed memory allocated for the port objects will, however, get freed when the pad controller unbinds from the driver. This can cause use-after-free errors down the road. Note that the device is deleted as part of the driver unbind operation, so there isn't much that can be done with it after that point, but the memory still needs to stay around to ensure none of the references are invalidated. One situation where this arises is when a VBUS supply is associated with a USB 2 or 3 port. When that supply is released using regulator_put() an SRCU call will queue the release of the device link connecting the port and the regulator after a grace period. This means that the regulator is going to keep on to the last reference of the port device even after the pad controller driver was unbound (which is when the memory backing the port device is freed). Fix this by allocating port objects using non-device-managed memory. Add release callbacks for these objects so that their memory gets freed when the last reference goes away. This decouples the port devices' lifetime from the "active" lifetime of the pad controller (i.e. the time during which the pad controller driver owns the device). Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-19 11:52:13 +01:00
phy: tegra: Fix regulator leak Devices are created for each port of the XUSB pad controller. Each USB 2 and USB 3 port can potentially have an associated VBUS power supply that needs to be removed when the device is removed. Since port devices never bind to a driver, the driver core will not get to perform the cleanup of device-managed resources that usually happens on driver unbind. Now, the driver core will also perform device-managed resource cleanup for driver-less devices when they are released. However, when a device link is created between the regulator and the port device, as part of regulator_get(), the regulator takes a reference to the port device and prevents it from being released unless regulator_put() is called, which will never happen. Avoid this by using the non-device-managed API and manually releasing the regulator reference when the port is unregistered. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-18 23:25:54 +01:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: Don't use device-managed API to allocate ports The device-managed allocation API doesn't work well with the life-cycle of device objects. Since ports have device objects allocated within, it can lead to situations where these devices need to stay around until after their parent pad controller has been unbound from its driver. The device-managed memory allocated for the port objects will, however, get freed when the pad controller unbinds from the driver. This can cause use-after-free errors down the road. Note that the device is deleted as part of the driver unbind operation, so there isn't much that can be done with it after that point, but the memory still needs to stay around to ensure none of the references are invalidated. One situation where this arises is when a VBUS supply is associated with a USB 2 or 3 port. When that supply is released using regulator_put() an SRCU call will queue the release of the device link connecting the port and the regulator after a grace period. This means that the regulator is going to keep on to the last reference of the port device even after the pad controller driver was unbound (which is when the memory backing the port device is freed). Fix this by allocating port objects using non-device-managed memory. Add release callbacks for these objects so that their memory gets freed when the last reference goes away. This decouples the port devices' lifetime from the "active" lifetime of the pad controller (i.e. the time during which the pad controller driver owns the device). Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-19 11:52:13 +01:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: Don't use device-managed API to allocate ports The device-managed allocation API doesn't work well with the life-cycle of device objects. Since ports have device objects allocated within, it can lead to situations where these devices need to stay around until after their parent pad controller has been unbound from its driver. The device-managed memory allocated for the port objects will, however, get freed when the pad controller unbinds from the driver. This can cause use-after-free errors down the road. Note that the device is deleted as part of the driver unbind operation, so there isn't much that can be done with it after that point, but the memory still needs to stay around to ensure none of the references are invalidated. One situation where this arises is when a VBUS supply is associated with a USB 2 or 3 port. When that supply is released using regulator_put() an SRCU call will queue the release of the device link connecting the port and the regulator after a grace period. This means that the regulator is going to keep on to the last reference of the port device even after the pad controller driver was unbound (which is when the memory backing the port device is freed). Fix this by allocating port objects using non-device-managed memory. Add release callbacks for these objects so that their memory gets freed when the last reference goes away. This decouples the port devices' lifetime from the "active" lifetime of the pad controller (i.e. the time during which the pad controller driver owns the device). Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-19 11:52:13 +01:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add Tegra194 support Add support for the XUSB pad controller found on Tegra194 SoCs. It is mostly similar to the same IP found on Tegra186, but the number of pads exposed differs, as do the programming sequences. Because most of the Tegra194 XUSB PADCTL registers definition and programming sequence are the same as Tegra186, Tegra194 XUSB PADCTL can share the same driver, xusb-tegra186.c, with Tegra186 XUSB PADCTL. Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. This patch adds a "maximum-speed" property to usb3 ports which can be used to specify the maximum supported speed for any particular USB 3.1 port. For a port that is not capable of SuperSpeedPlus, "maximum-speed" property should carry "super-speed". Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-02-12 14:11:30 +08:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: Don't use device-managed API to allocate ports The device-managed allocation API doesn't work well with the life-cycle of device objects. Since ports have device objects allocated within, it can lead to situations where these devices need to stay around until after their parent pad controller has been unbound from its driver. The device-managed memory allocated for the port objects will, however, get freed when the pad controller unbinds from the driver. This can cause use-after-free errors down the road. Note that the device is deleted as part of the driver unbind operation, so there isn't much that can be done with it after that point, but the memory still needs to stay around to ensure none of the references are invalidated. One situation where this arises is when a VBUS supply is associated with a USB 2 or 3 port. When that supply is released using regulator_put() an SRCU call will queue the release of the device link connecting the port and the regulator after a grace period. This means that the regulator is going to keep on to the last reference of the port device even after the pad controller driver was unbound (which is when the memory backing the port device is freed). Fix this by allocating port objects using non-device-managed memory. Add release callbacks for these objects so that their memory gets freed when the last reference goes away. This decouples the port devices' lifetime from the "active" lifetime of the pad controller (i.e. the time during which the pad controller driver owns the device). Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-19 11:52:13 +01:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: Don't use device-managed API to allocate ports The device-managed allocation API doesn't work well with the life-cycle of device objects. Since ports have device objects allocated within, it can lead to situations where these devices need to stay around until after their parent pad controller has been unbound from its driver. The device-managed memory allocated for the port objects will, however, get freed when the pad controller unbinds from the driver. This can cause use-after-free errors down the road. Note that the device is deleted as part of the driver unbind operation, so there isn't much that can be done with it after that point, but the memory still needs to stay around to ensure none of the references are invalidated. One situation where this arises is when a VBUS supply is associated with a USB 2 or 3 port. When that supply is released using regulator_put() an SRCU call will queue the release of the device link connecting the port and the regulator after a grace period. This means that the regulator is going to keep on to the last reference of the port device even after the pad controller driver was unbound (which is when the memory backing the port device is freed). Fix this by allocating port objects using non-device-managed memory. Add release callbacks for these objects so that their memory gets freed when the last reference goes away. This decouples the port devices' lifetime from the "active" lifetime of the pad controller (i.e. the time during which the pad controller driver owns the device). Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-19 11:52:13 +01:00
phy: tegra: Fix regulator leak Devices are created for each port of the XUSB pad controller. Each USB 2 and USB 3 port can potentially have an associated VBUS power supply that needs to be removed when the device is removed. Since port devices never bind to a driver, the driver core will not get to perform the cleanup of device-managed resources that usually happens on driver unbind. Now, the driver core will also perform device-managed resource cleanup for driver-less devices when they are released. However, when a device link is created between the regulator and the port device, as part of regulator_get(), the regulator takes a reference to the port device and prevents it from being released unless regulator_put() is called, which will never happen. Avoid this by using the non-device-managed API and manually releasing the regulator reference when the port is unregistered. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-18 23:25:54 +01:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add sleepwalk and suspend/resume This commit adds sleepwalk/wake and suspend/resume interfaces to Tegra XUSB PHY driver. Tegra XUSB host controller driver makes use of sleepwalk functions to enable/disable sleepwalk circuit which is in always-on partition and can respond to USB resume signals when controller is not powered. Sleepwalk can be enabled/disabled for any USB UPHY individually. - tegra_xusb_padctl_enable_phy_sleepwalk() - tegra_xusb_padctl_disable_phy_sleepwalk() Tegra XUSB host controller driver makes use of wake functions to enable/disable/query wake circuit which is in always-on partition can wake system up when USB resume happens. Wake circuit can be enabled/disabled for any USB PHY individually. - tegra_xusb_padctl_enable_phy_wake() - tegra_xusb_padctl_disable_phy_wake() - tegra_xusb_padctl_remote_wake_detected() This commit also adds two system suspend stubs that can be used to save and restore XUSB PADCTL context during system suspend and resume. - tegra_xusb_padctl_suspend_noirq() - tegra_xusb_padctl_resume_noirq() Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-By: Vinod Koul <vkoul@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-20 15:34:06 +08:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add vbus override support on Tegra210 Tegra XUSB device control driver needs to control vbus override during its operations, add API for the support. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-10-18 15:08:08 +05:30
phy: tegra: xusb: add utmi pad power on/down ops Add utmi_pad_power_on/down ops for each SOC instead of exporting tegra_phy_xusb_utmi_pad_power_on/down directly for Tegra186 chip. Signed-off-by: BH Hsieh <bhsieh@nvidia.com> Signed-off-by: Jim Lin <jilin@nvidia.com> Link: https://lore.kernel.org/r/20220816082353.13390-2-jilin@nvidia.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-08-16 16:23:52 +08:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add support for power supplies Support enabling various supplies needed to provide power to the PLLs and logic used to drive the USB, PCI and SATA pads. Reviewed-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-02-21 16:46:33 +01:00
phy: tegra: xusb: Add Tegra194 support Add support for the XUSB pad controller found on Tegra194 SoCs. It is mostly similar to the same IP found on Tegra186, but the number of pads exposed differs, as do the programming sequences. Because most of the Tegra194 XUSB PADCTL registers definition and programming sequence are the same as Tegra186, Tegra194 XUSB PADCTL can share the same driver, xusb-tegra186.c, with Tegra186 XUSB PADCTL. Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. This patch adds a "maximum-speed" property to usb3 ports which can be used to specify the maximum supported speed for any particular USB 3.1 port. For a port that is not capable of SuperSpeedPlus, "maximum-speed" property should carry "super-speed". Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-02-12 14:11:30 +08:00
phy: tegra: xusb: Add usb3 port fake support on Tegra210 On Tegra210, usb2 only otg/peripheral ports dont work in device mode. They need an assosciated usb3 port to work in device mode. Identify an unused usb3 port and assign it as a fake USB3 port to USB2 only port whose mode is otg/peripheral. Based on work by BH Hsieh <bhsieh@nvidia.com>. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-10-18 15:08:07 +05:30
phy: tegra: xusb: Add Tegra234 support Add support for the XUSB pad controller found on Tegra234 SoCs. It is mostly similar to the same IP found on Tegra194, because most of the Tegra234 XUSB PADCTL registers definition and programming sequence are the same as Tegra194, Tegra234 XUSB PADCTL can share the same driver with Tegra186 and Tegra194 XUSB PADCTL. Introduce a new feature, USB2 HW tracking, for Tegra234. The feature is to enable HW periodical PAD tracking which measure and capture the electric parameters of USB2.0 PAD. Signed-off-by: Sing-Han Chen <singhanc@nvidia.com> Co-developed-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230111110450.24617-6-jonathanh@nvidia.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-01-11 11:04:49 +00:00
phy: tegra: xusb: Support sleepwalk for Tegra234 Add new registers programming in sleepwalk sequence for Tegra234: MASTER_ENABLE_A/B/C/D in XUSB_AO_UTMIP_SLEEPWALK. Signed-off-by: Henry Lin <henryl@nvidia.com> Signed-off-by: Haotien Hsu <haotienh@nvidia.com> Link: https://lore.kernel.org/r/20230309061708.4156383-1-haotienh@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-09 14:17:08 +08:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add support for power supplies Support enabling various supplies needed to provide power to the PLLs and logic used to drive the USB, PCI and SATA pads. Reviewed-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-02-21 16:46:33 +01:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add Tegra234 support Add support for the XUSB pad controller found on Tegra234 SoCs. It is mostly similar to the same IP found on Tegra194, because most of the Tegra234 XUSB PADCTL registers definition and programming sequence are the same as Tegra194, Tegra234 XUSB PADCTL can share the same driver with Tegra186 and Tegra194 XUSB PADCTL. Introduce a new feature, USB2 HW tracking, for Tegra234. The feature is to enable HW periodical PAD tracking which measure and capture the electric parameters of USB2.0 PAD. Signed-off-by: Sing-Han Chen <singhanc@nvidia.com> Co-developed-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230111110450.24617-6-jonathanh@nvidia.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-01-11 11:04:49 +00:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00
phy: tegra: xusb: Add Tegra186 support Add support for the XUSB pad controller found on Tegra186 SoCs. It is mostly similar to the same IP found on earlier chips, but the number of pads exposed differs, as do the programming sequences. Note that the DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL power supplies of the XUSB pad controller require strict power sequencing and are therefore controlled by the PMIC on Tegra186. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> [dan.carpenter@oracle.com: Fix testing the wrong variable in probe()] Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> [yuehaibing@huawei.com: Make two functions static to fix sparse warning] Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-02-21 16:46:34 +01:00
phy: tegra: xusb: Add Tegra194 support Add support for the XUSB pad controller found on Tegra194 SoCs. It is mostly similar to the same IP found on Tegra186, but the number of pads exposed differs, as do the programming sequences. Because most of the Tegra194 XUSB PADCTL registers definition and programming sequence are the same as Tegra186, Tegra194 XUSB PADCTL can share the same driver, xusb-tegra186.c, with Tegra186 XUSB PADCTL. Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is possible for some platforms have long signal trace that could not provide sufficient electrical environment for Gen 2 speed. This patch adds a "maximum-speed" property to usb3 ports which can be used to specify the maximum supported speed for any particular USB 3.1 port. For a port that is not capable of SuperSpeedPlus, "maximum-speed" property should carry "super-speed". Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-02-12 14:11:30 +08:00
phy: tegra: xusb: Add Tegra234 support Add support for the XUSB pad controller found on Tegra234 SoCs. It is mostly similar to the same IP found on Tegra194, because most of the Tegra234 XUSB PADCTL registers definition and programming sequence are the same as Tegra194, Tegra234 XUSB PADCTL can share the same driver with Tegra186 and Tegra194 XUSB PADCTL. Introduce a new feature, USB2 HW tracking, for Tegra234. The feature is to enable HW periodical PAD tracking which measure and capture the electric parameters of USB2.0 PAD. Signed-off-by: Sing-Han Chen <singhanc@nvidia.com> Co-developed-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230111110450.24617-6-jonathanh@nvidia.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-01-11 11:04:49 +00:00
phy: Add Tegra XUSB pad controller support Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-11-11 18:24:21 +01:00