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linux/drivers/thunderbolt/lc.c

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thunderbolt: Move LC specific functionality into a separate file We will be adding more link controller functionality in subsequent patches and it does not make sense to keep all that in switch.c, so separate LC functionality into its own file. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-01-09 16:42:12 +02:00
thunderbolt: Introduce tb_port_reset() Introduce a function that issues Downstream Port Reset to a USB4 port. This supports Thunderbolt 2, 3 and USB4 routers. Signed-off-by: Sanath S <Sanath.S@amd.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2024-01-13 11:39:57 +02:00
thunderbolt: Move LC specific functionality into a separate file We will be adding more link controller functionality in subsequent patches and it does not make sense to keep all that in switch.c, so separate LC functionality into its own file. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-01-09 16:42:12 +02:00
thunderbolt: Configure lanes when switch is initialized Thunderbolt 2 devices and beyond need to have additional bits set in link controller specific registers. This includes two bits in LC_SX_CTRL that tell the link controller which lane is connected and whether it is upstream facing or not. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-10-11 12:33:08 +03:00
thunderbolt: Introduce tb_port_reset() Introduce a function that issues Downstream Port Reset to a USB4 port. This supports Thunderbolt 2, 3 and USB4 routers. Signed-off-by: Sanath S <Sanath.S@amd.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2024-01-13 11:39:57 +02:00
thunderbolt: Set port configured for both ends of the link Both ends of the link needs to have this set. Otherwise the link is not re-established properly after sleep. Now since it is possible to have mixed USB4 and Thunderbolt 1, 2 and 3 devices we need to split the link configuration functionality to happen per port so we can pick the correct implementation. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-02 12:42:44 +03:00
thunderbolt: Configure lanes when switch is initialized Thunderbolt 2 devices and beyond need to have additional bits set in link controller specific registers. This includes two bits in LC_SX_CTRL that tell the link controller which lane is connected and whether it is upstream facing or not. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-10-11 12:33:08 +03:00
thunderbolt: Set port configured for both ends of the link Both ends of the link needs to have this set. Otherwise the link is not re-established properly after sleep. Now since it is possible to have mixed USB4 and Thunderbolt 1, 2 and 3 devices we need to split the link configuration functionality to happen per port so we can pick the correct implementation. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-02 12:42:44 +03:00
thunderbolt: Configure lanes when switch is initialized Thunderbolt 2 devices and beyond need to have additional bits set in link controller specific registers. This includes two bits in LC_SX_CTRL that tell the link controller which lane is connected and whether it is upstream facing or not. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-10-11 12:33:08 +03:00
thunderbolt: Set port configured for both ends of the link Both ends of the link needs to have this set. Otherwise the link is not re-established properly after sleep. Now since it is possible to have mixed USB4 and Thunderbolt 1, 2 and 3 devices we need to split the link configuration functionality to happen per port so we can pick the correct implementation. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-02 12:42:44 +03:00
thunderbolt: Configure lanes when switch is initialized Thunderbolt 2 devices and beyond need to have additional bits set in link controller specific registers. This includes two bits in LC_SX_CTRL that tell the link controller which lane is connected and whether it is upstream facing or not. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-10-11 12:33:08 +03:00
thunderbolt: Set port configured for both ends of the link Both ends of the link needs to have this set. Otherwise the link is not re-established properly after sleep. Now since it is possible to have mixed USB4 and Thunderbolt 1, 2 and 3 devices we need to split the link configuration functionality to happen per port so we can pick the correct implementation. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-02 12:42:44 +03:00
thunderbolt: Configure lanes when switch is initialized Thunderbolt 2 devices and beyond need to have additional bits set in link controller specific registers. This includes two bits in LC_SX_CTRL that tell the link controller which lane is connected and whether it is upstream facing or not. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-10-11 12:33:08 +03:00
thunderbolt: Set port configured for both ends of the link Both ends of the link needs to have this set. Otherwise the link is not re-established properly after sleep. Now since it is possible to have mixed USB4 and Thunderbolt 1, 2 and 3 devices we need to split the link configuration functionality to happen per port so we can pick the correct implementation. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-02 12:42:44 +03:00
thunderbolt: Configure lanes when switch is initialized Thunderbolt 2 devices and beyond need to have additional bits set in link controller specific registers. This includes two bits in LC_SX_CTRL that tell the link controller which lane is connected and whether it is upstream facing or not. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-10-11 12:33:08 +03:00
thunderbolt: Set port configured for both ends of the link Both ends of the link needs to have this set. Otherwise the link is not re-established properly after sleep. Now since it is possible to have mixed USB4 and Thunderbolt 1, 2 and 3 devices we need to split the link configuration functionality to happen per port so we can pick the correct implementation. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-02 12:42:44 +03:00
thunderbolt: Configure lanes when switch is initialized Thunderbolt 2 devices and beyond need to have additional bits set in link controller specific registers. This includes two bits in LC_SX_CTRL that tell the link controller which lane is connected and whether it is upstream facing or not. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-10-11 12:33:08 +03:00
thunderbolt: Set port configured for both ends of the link Both ends of the link needs to have this set. Otherwise the link is not re-established properly after sleep. Now since it is possible to have mixed USB4 and Thunderbolt 1, 2 and 3 devices we need to split the link configuration functionality to happen per port so we can pick the correct implementation. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-02 12:42:44 +03:00
thunderbolt: Configure lanes when switch is initialized Thunderbolt 2 devices and beyond need to have additional bits set in link controller specific registers. This includes two bits in LC_SX_CTRL that tell the link controller which lane is connected and whether it is upstream facing or not. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-10-11 12:33:08 +03:00
thunderbolt: Set port configured for both ends of the link Both ends of the link needs to have this set. Otherwise the link is not re-established properly after sleep. Now since it is possible to have mixed USB4 and Thunderbolt 1, 2 and 3 devices we need to split the link configuration functionality to happen per port so we can pick the correct implementation. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-02 12:42:44 +03:00
thunderbolt: Configure lanes when switch is initialized Thunderbolt 2 devices and beyond need to have additional bits set in link controller specific registers. This includes two bits in LC_SX_CTRL that tell the link controller which lane is connected and whether it is upstream facing or not. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-10-11 12:33:08 +03:00
thunderbolt: Set port configured for both ends of the link Both ends of the link needs to have this set. Otherwise the link is not re-established properly after sleep. Now since it is possible to have mixed USB4 and Thunderbolt 1, 2 and 3 devices we need to split the link configuration functionality to happen per port so we can pick the correct implementation. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-02 12:42:44 +03:00
thunderbolt: Configure lanes when switch is initialized Thunderbolt 2 devices and beyond need to have additional bits set in link controller specific registers. This includes two bits in LC_SX_CTRL that tell the link controller which lane is connected and whether it is upstream facing or not. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-10-11 12:33:08 +03:00
thunderbolt: Set port configured for both ends of the link Both ends of the link needs to have this set. Otherwise the link is not re-established properly after sleep. Now since it is possible to have mixed USB4 and Thunderbolt 1, 2 and 3 devices we need to split the link configuration functionality to happen per port so we can pick the correct implementation. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-02 12:42:44 +03:00
thunderbolt: Configure lanes when switch is initialized Thunderbolt 2 devices and beyond need to have additional bits set in link controller specific registers. This includes two bits in LC_SX_CTRL that tell the link controller which lane is connected and whether it is upstream facing or not. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-10-11 12:33:08 +03:00
thunderbolt: Set sleep bit when suspending switch Thunderbolt 2 devices and beyond link controller needs to be notified when a switch is going to be suspended by setting bit 31 in LC_SX_CTRL register. Add this functionality to the software connection manager. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-01-09 17:25:43 +02:00
thunderbolt: Configure port for XDomain When the port is connected to another host it should be marked as such in the USB4 port capability. This information is used by the router during sleep and wakeup. Also do the same for legacy switches via link controller vendor specific registers. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-04-09 14:23:32 +03:00
thunderbolt: Start lane initialization after sleep USB4 spec says that for TBT3 compatible device routers the connection manager needs to set SLI (Start Lane Initialization) to get the lanes that were not connected back to functional state after sleep. Same needs to be done if the link was XDomain. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Yehezkel Bernat <YehezkelShB@gmail.com>
2020-11-26 12:52:43 +03:00
thunderbolt: Enable CL0s for Intel Titan Ridge Low power link states (called collectively CLx) are used to reduce transmitter and receiver power when a high-speed lane is idle. The simplest one being called CL0s. Follow what we already do for USB4 device routers and enable CL0s for Intel Titan Ridge device router too. This allows better thermal management. Signed-off-by: Gil Fine <gil.fine@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-12-17 03:16:43 +02:00
thunderbolt: Add internal xHCI connect flows for Thunderbolt 3 devices Both Alpine Ridge and Titan Ridge require special flows in order to activate the internal xHCI controller when there is USB device connected to the downstream type-C port. This implements the missing flows for both. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-01-07 13:00:47 +02:00
thunderbolt: Enable wakes from system suspend In order for the router and the whole domain to wake up from system suspend states we need to enable wakes for the connected routers. For device routers we enable wakes from PCIe and USB 3.x. This allows devices such as keyboards connected to USB 3.x hub that is tunneled to wake the system up as expected. For all routers we enabled wake on USB4 for each connected ports. This is used to propagate the wake from router to another. Do the same for legacy routers through link controller vendor specific registers as documented in USB4 spec chapter 13. While there correct kernel-doc of usb4_switch_set_sleep() -- it does not enable wakes instead there is a separate function (usb4_switch_set_wake()) that does. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-06 18:36:07 +02:00
thunderbolt: Add wake from DisplayPort Latest USB4 spec added a new wake bit for DisplayPort so add this to the driver when runtime suspending. This way wake up the domain when a new monitor is plugged in to any of the device routers. Also do the same for pre-USB4 devices through the link controller registers as documented in chapter 13 of the USB4 spec. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-01-14 16:44:17 +02:00
thunderbolt: Enable wakes from system suspend In order for the router and the whole domain to wake up from system suspend states we need to enable wakes for the connected routers. For device routers we enable wakes from PCIe and USB 3.x. This allows devices such as keyboards connected to USB 3.x hub that is tunneled to wake the system up as expected. For all routers we enabled wake on USB4 for each connected ports. This is used to propagate the wake from router to another. Do the same for legacy routers through link controller vendor specific registers as documented in USB4 spec chapter 13. While there correct kernel-doc of usb4_switch_set_sleep() -- it does not enable wakes instead there is a separate function (usb4_switch_set_wake()) that does. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-06 18:36:07 +02:00
thunderbolt: Add wake from DisplayPort Latest USB4 spec added a new wake bit for DisplayPort so add this to the driver when runtime suspending. This way wake up the domain when a new monitor is plugged in to any of the device routers. Also do the same for pre-USB4 devices through the link controller registers as documented in chapter 13 of the USB4 spec. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-01-14 16:44:17 +02:00
thunderbolt: Enable wakes from system suspend In order for the router and the whole domain to wake up from system suspend states we need to enable wakes for the connected routers. For device routers we enable wakes from PCIe and USB 3.x. This allows devices such as keyboards connected to USB 3.x hub that is tunneled to wake the system up as expected. For all routers we enabled wake on USB4 for each connected ports. This is used to propagate the wake from router to another. Do the same for legacy routers through link controller vendor specific registers as documented in USB4 spec chapter 13. While there correct kernel-doc of usb4_switch_set_sleep() -- it does not enable wakes instead there is a separate function (usb4_switch_set_wake()) that does. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-12-06 18:36:07 +02:00
thunderbolt: Set sleep bit when suspending switch Thunderbolt 2 devices and beyond link controller needs to be notified when a switch is going to be suspended by setting bit 31 in LC_SX_CTRL register. Add this functionality to the software connection manager. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-01-09 17:25:43 +02:00
thunderbolt: Add support for lane bonding Lane bonding allows aggregating two 10/20 Gb/s (depending on the generation) lanes into a single 20/40 Gb/s bonded link. This allows sharing the full bandwidth more efficiently. In order to establish lane bonding we need to check that lane bonding is possible through link controller and that both ends of the link actually supports 2x widths. This also means that all the paths should be established through the primary port so update tb_path_alloc() to handle this as well. Lane bonding is supported starting from Falcon Ridge (2nd generation) controllers. We also expose the current speed and number of lanes under each device except the host router following similar attribute naming than USB bus. Expose speed and number of lanes for both directions to allow possibility of asymmetric link in the future. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-03-21 19:03:00 +02:00
thunderbolt: Add Display Port adapter pairing and resource management To perform proper Display Port tunneling for Thunderbolt 3 devices we need to allocate DP resources for DP IN port before they can be used. The reason for this is that the user can also connect a monitor directly to the Type-C ports in which case the Thunderbolt controller acts as re-driver for Display Port (no tunneling takes place) taking the DP sinks away from the connection manager. This allocation is done using special sink allocation registers available through the link controller. We can pair DP IN to DP OUT only if * DP IN has sink allocated via link controller * DP OUT port receives hotplug event For DP IN adapters (only for the host router) we first query whether there is DP resource available (it may be the previous instance of the driver for example already allocated it) and if it is we add it to the list. We then update the list when after each plug/unplug event to a DP IN/OUT adapter. Each time the list is updated we try to find additional DP IN <-> DP OUT pairs for tunnel establishment. This strategy also makes it possible to establish another tunnel in case there are 3 monitors connected and one gets unplugged releasing the DP IN adapter for the new tunnel. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-03-26 15:52:30 +03:00
thunderbolt: Add support for authenticate on disconnect Some external devices can support completing thunderbolt authentication when they are unplugged. For this to work though, the link controller must remain operational. The only device known to support this right now is the Dell WD19TB, so add a quirk for this. Signed-off-by: Mario Limonciello <mario.limonciello@dell.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-06-23 11:14:29 -05:00