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linux/drivers/dma/altera-msgdma.c

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dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use IRQ-safe spinlock calls in the error paths as well The patch edf10919 [dmaengine: altera: fix spinlock usage] missed to change 2 occurrences of spin_unlock_bh() to spin_unlock_irqrestore(). This patch fixes this by moving to the IRQ-safe call in the error paths as well. Fixes: edf10919 (dmaengine: altera: fix spinlock usage) Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Sylvain Lesne <lesne@alse-fr.com> [add fixes tag and fix typo in log] Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-10-16 08:13:53 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use IRQ-safe spinlock calls in the error paths as well The patch edf10919 [dmaengine: altera: fix spinlock usage] missed to change 2 occurrences of spin_unlock_bh() to spin_unlock_irqrestore(). This patch fixes this by moving to the IRQ-safe call in the error paths as well. Fixes: edf10919 (dmaengine: altera: fix spinlock usage) Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Sylvain Lesne <lesne@alse-fr.com> [add fixes tag and fix typo in log] Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-10-16 08:13:53 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: altera: fix response FIFO emptying Commit 6084fc2ec478 ("dmaengine: altera: Use macros instead of structs to describe the registers") introduced a minus sign before a register offset. This leads to soft-locks of the DMA controller, since reading the last status byte is required to pop the response from the FIFO. Failing to do so will lead to a full FIFO, which means that the DMA controller will stop processing descriptors. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:00 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: fix spinlock usage Since this lock is acquired in both process and IRQ context, failing to to disable IRQs when trying to acquire the lock in process context can lead to deadlocks. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-18 13:08:01 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: altera: Use macros instead of structs to describe the registers This patch moves from a struct declaration for the DMA controller registers to macros with offests to the base address. This is mainly done to remove the sparse warnings, since the function parameter of ioread32/iowrite32 is "void __iomem *" instead of a pointer to struct members. With this patch applied, no sparse warning is seen anymore. Please note that the struct for the descriptors is still kept in place, as the code largely accesses the struct members as internal variables before the complete struct is copied into the descriptor FIFO of the DMA controller. Additionally this patch also removes two warnings "variable xxx set but not used" seen when compiling with "W=1". The registers need to be read to flush the response FIFO, but nothing needs to be done with them. So the code is correct here and the warning is a false one. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-26 09:59:07 +02:00
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00