2009-10-26 13:06:31 -07:00
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2015-10-11 11:26:26 +02:00
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2009-10-26 13:06:31 -07:00
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2015-10-07 09:55:28 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2014-01-22 22:38:57 +01:00
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2015-10-11 11:55:00 +02:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2014-01-22 22:38:57 +01:00
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2012-07-13 00:57:26 +02:00
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2014-01-22 22:38:57 +01:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2015-10-11 11:55:00 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2015-10-11 11:55:00 +02:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2014-01-22 12:21:16 +01:00
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2015-10-11 11:26:26 +02:00
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2014-01-22 12:21:16 +01:00
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2009-10-26 13:06:31 -07:00
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2011-08-25 17:21:31 +00:00
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2009-10-26 13:06:31 -07:00
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2015-12-08 09:49:17 +01:00
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2009-10-26 13:06:31 -07:00
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2011-08-25 17:18:08 +00:00
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2009-10-26 13:06:31 -07:00
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2011-08-25 17:18:08 +00:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2015-09-28 21:46:35 +02:00
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2014-04-23 11:52:10 +02:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2013-06-22 14:10:59 +02:00
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2012-07-13 00:57:26 +02:00
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|
drm: implement experimental render nodes
Render nodes provide an API for userspace to use non-privileged GPU
commands without any running DRM-Master. It is useful for offscreen
rendering, GPGPU clients, and normal render clients which do not perform
modesetting.
Compared to legacy clients, render clients no longer need any
authentication to perform client ioctls. Instead, user-space controls
render/client access to GPUs via filesystem access-modes on the
render-node. Once a render-node was opened, a client has full access to
the client/render operations on the GPU. However, no modesetting or ioctls
that affect global state are allowed on render nodes.
To prevent privilege-escalation, drivers must explicitly state that they
support render nodes. They must mark their render-only ioctls as
DRM_RENDER_ALLOW so render clients can use them. Furthermore, they must
support clients without any attached master.
If filesystem access-modes are not enough for fine-grained access control
to render nodes (very unlikely, considering the versaitlity of FS-ACLs),
you may still fall-back to fd-passing from server to client (which allows
arbitrary access-control). However, note that revoking access is
currently impossible and unlikely to get implemented.
Note: Render clients no longer have any associated DRM-Master as they are
supposed to be independent of any server state. DRM core highly depends on
file_priv->master to be non-NULL for modesetting/ctx/etc. commands.
Therefore, drivers must be very careful to not require DRM-Master if they
support DRIVER_RENDER.
So far render-nodes are protected by "drm_rnodes". As long as this
module-parameter is not set to 1, a driver will not create render nodes.
This allows us to experiment with the API a bit before we stabilize it.
v2: drop insecure GEM_FLINK to force use of dmabuf
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-08-25 18:29:00 +02:00
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2014-12-18 16:01:50 -05:00
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2012-07-13 00:57:26 +02:00
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2014-05-19 13:39:07 +02:00
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2015-09-28 21:46:35 +02:00
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2014-08-08 11:33:12 +02:00
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2014-05-19 13:39:07 +02:00
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2012-07-13 00:57:26 +02:00
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2013-06-22 14:10:59 +02:00
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2012-07-13 00:57:26 +02:00
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2013-06-22 14:10:59 +02:00
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2013-11-03 21:09:27 +01:00
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2013-06-22 14:10:59 +02:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2015-09-28 21:46:35 +02:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2013-05-08 16:56:16 -07:00
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2012-07-13 00:57:26 +02:00
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2014-05-15 13:54:06 -07:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2014-11-03 14:45:44 +01:00
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2009-10-26 13:06:31 -07:00
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2014-11-03 14:45:44 +01:00
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2012-07-13 00:57:26 +02:00
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2014-11-03 14:45:44 +01:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2014-11-03 14:45:44 +01:00
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2012-07-13 00:57:26 +02:00
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2014-11-03 14:45:44 +01:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2015-10-22 19:11:27 +02:00
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2012-07-13 00:57:26 +02:00
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2015-10-22 19:11:29 +02:00
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2012-07-13 00:57:26 +02:00
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2014-11-03 14:45:44 +01:00
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2012-07-13 00:57:26 +02:00
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2015-10-22 19:11:29 +02:00
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2012-07-13 00:57:26 +02:00
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2014-11-03 14:45:44 +01:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2015-10-22 19:11:27 +02:00
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2014-01-21 12:39:00 +01:00
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2015-10-22 19:11:27 +02:00
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2014-11-03 14:45:44 +01:00
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2014-01-22 12:28:42 +01:00
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2014-11-03 14:45:44 +01:00
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2014-01-22 18:46:33 +01:00
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2014-11-03 14:45:44 +01:00
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2014-01-22 18:46:33 +01:00
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2014-11-03 14:45:44 +01:00
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2014-01-22 18:46:33 +01:00
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2014-11-03 14:45:44 +01:00
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2014-01-22 19:16:30 +01:00
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2014-11-03 14:45:44 +01:00
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2014-01-23 00:31:48 +01:00
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2014-11-03 14:45:44 +01:00
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2014-01-23 00:31:48 +01:00
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2014-11-03 14:45:44 +01:00
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2014-01-23 00:31:48 +01:00
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2014-11-03 14:45:44 +01:00
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2014-01-23 00:39:13 +01:00
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2014-11-03 14:45:44 +01:00
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2014-11-03 13:56:55 +01:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2014-01-23 15:06:15 +01:00
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2014-01-23 20:05:00 +01:00
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2014-01-23 15:06:15 +01:00
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2014-07-25 21:30:38 +02:00
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2015-12-04 09:45:57 +01:00
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2014-01-23 15:06:15 +01:00
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2009-10-26 13:06:31 -07:00
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2015-12-08 09:49:19 +01:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2014-01-21 12:01:41 +01:00
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2012-07-13 00:57:26 +02:00
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2013-01-04 22:31:20 +01:00
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2014-01-23 21:57:37 +01:00
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2013-01-04 22:31:20 +01:00
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2014-01-23 21:57:37 +01:00
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2012-07-13 00:57:26 +02:00
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2014-01-21 12:01:41 +01:00
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2012-07-13 00:57:26 +02:00
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2013-01-04 22:31:20 +01:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2014-04-01 15:22:43 -07:00
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2014-12-17 16:13:17 +01:00
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2015-12-04 09:46:00 +01:00
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2014-04-01 15:22:43 -07:00
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2012-07-13 00:57:26 +02:00
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2014-04-01 15:22:43 -07:00
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2012-07-13 00:57:26 +02:00
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2014-04-01 15:22:43 -07:00
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2012-07-13 00:57:26 +02:00
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2014-04-01 15:22:43 -07:00
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2012-07-13 00:57:26 +02:00
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2014-05-29 16:57:41 +01:00
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2012-07-13 00:57:26 +02:00
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2014-05-29 16:57:41 +01:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2014-05-29 16:57:41 +01:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-12-02 00:09:18 +01:00
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2014-10-27 16:54:27 +01:00
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2012-12-02 00:09:18 +01:00
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2013-11-19 12:10:12 -05:00
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2009-10-26 13:06:31 -07:00
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2012-11-01 14:45:15 +01:00
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2009-10-26 13:06:31 -07:00
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2012-11-01 14:45:15 +01:00
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2009-10-26 13:06:31 -07:00
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2014-04-01 15:22:43 -07:00
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2012-07-13 00:57:26 +02:00
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2014-04-01 15:22:43 -07:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2014-11-06 20:53:29 +01:00
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2014-11-25 20:29:46 -05:00
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2014-11-06 20:53:29 +01:00
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2012-11-01 14:45:16 +01:00
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2015-12-04 09:45:44 +01:00
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2014-11-06 20:53:29 +01:00
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2012-11-01 14:45:16 +01:00
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2015-12-04 09:45:46 +01:00
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2012-11-01 14:45:16 +01:00
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2014-11-06 20:53:29 +01:00
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2014-04-10 10:51:11 +02:00
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2012-11-01 14:45:16 +01:00
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2012-11-01 14:45:17 +01:00
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2013-01-20 22:13:14 +01:00
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2016-05-11 18:09:18 +02:00
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2012-11-01 14:45:17 +01:00
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2012-11-01 14:45:18 +01:00
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drm: Add helper for DP++ adaptors
Add a helper which aids in the identification of DP dual mode
(aka. DP++) adaptors. There are several types of adaptors
specified: type 1 DVI, type 1 HDMI, type 2 DVI, type 2 HDMI
Type 1 adaptors have a max TMDS clock limit of 165MHz, type 2 adaptors
may go as high as 300MHz and they provide a register informing the
source device what the actual limit is. Supposedly also type 1 adaptors
may optionally implement this register. This TMDS clock limit is the
main reason why we need to identify these adaptors.
Type 1 adaptors provide access to their internal registers and the sink
DDC bus through I2C. Type 2 adaptors provide this access both via I2C
and I2C-over-AUX. A type 2 source device may choose to implement either
of these methods. If a source device implements the I2C-over-AUX
method, then the driver will obviously need specific support for such
adaptors since the port is driven like an HDMI port, but DDC
communication happes over the AUX channel.
This helper should be enough to identify the adaptor type (some
type 1 DVI adaptors may be a slight exception) and the maximum TMDS
clock limit. Another feature that may be available is control over
the TMDS output buffers on the adaptor, possibly allowing for some
power saving when the TMDS link is down.
Other user controllable features that may be available in the adaptors
are downstream i2c bus speed control when using i2c-over-aux, and
some control over the CEC pin. I chose not to provide any helper
functions for those since I have no use for them in i915 at this time.
The rest of the registers in the adaptor are mostly just information,
eg. IEEE OUI, hardware and firmware revision, etc.
v2: Pass adaptor type to helper functions to ease driver implementation
Fix a bunch of typoes (Paulo)
Add DRM_DP_DUAL_MODE_UNKNOWN for the case where we don't (yet) know
the type (Paulo)
Reject 0x00 and 0xff DP_DUAL_MODE_MAX_TMDS_CLOCK values (Paulo)
Adjust drm_dp_dual_mode_detect() type2 vs. type1 detection to
ease future LSPCON enabling
Remove the unused DP_DUAL_MODE_LAST_RESERVED define
v3: Fix kernel doc function argument descriptions (Jani)
s/NONE/UNKNOWN/ in drm_dp_dual_mode_detect() docs
Add kernel doc for enum drm_dp_dual_mode_type
Actually build the docs
Fix more typoes
v4: Adjust code indentation of type2 adaptor detection (Shashank)
Add debug messages for failurs cases (Shashank)
v5: EXPORT_SYMBOL(drm_dp_dual_mode_read) (Paulo)
Cc: stable@vger.kernel.org
Cc: Tore Anderson <tore@fud.no>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> (v4)
Link: http://patchwork.freedesktop.org/patch/msgid/1462542412-25533-1-git-send-email-ville.syrjala@linux.intel.com
(cherry picked from commit ede53344dbfd1dd43bfd73eb6af743d37c56a7c3)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-05-06 16:46:52 +03:00
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2014-06-05 14:01:32 +10:00
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2014-08-05 10:41:13 +02:00
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2012-11-01 14:45:18 +01:00
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2013-01-14 09:00:31 +01:00
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2013-05-08 17:16:45 +03:00
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2013-08-07 14:41:54 -04:00
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2013-05-08 17:16:45 +03:00
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2014-01-22 18:26:16 +01:00
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2014-04-01 15:22:43 -07:00
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2014-11-06 20:53:29 +01:00
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2014-04-01 15:22:43 -07:00
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2014-10-20 16:17:17 +10:00
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2015-05-21 11:03:17 +05:30
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2016-05-06 16:01:37 +02:00
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2015-05-21 11:03:17 +05:30
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2016-05-06 16:01:37 +02:00
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2015-05-21 11:03:17 +05:30
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2016-05-06 16:01:37 +02:00
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2015-05-21 11:03:17 +05:30
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2016-05-06 16:01:37 +02:00
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2009-10-26 13:06:31 -07:00
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2013-06-22 16:10:30 +02:00
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2014-05-15 13:54:06 -07:00
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2013-06-22 16:10:30 +02:00
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Documentation: drm: describing drm properties exposed by various drivers
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du
v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]
v4: Removed whitespace warnings and minor nits. [Randy's review comments]
v5: Restructured output for ENUM properties
v6: Review comments on formatting the table. [Laurent's review comments]
v7: Minor restructuring. [Laurent's review comments]
Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-03-11 19:55:29 +05:30
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2016-02-26 17:05:00 +00:00
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2016-05-02 15:13:01 -04:00
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2015-05-28 16:35:07 +05:30
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2016-05-02 15:13:01 -04:00
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2014-12-18 16:01:54 -05:00
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|
Documentation: drm: describing drm properties exposed by various drivers
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du
v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]
v4: Removed whitespace warnings and minor nits. [Randy's review comments]
v5: Restructured output for ENUM properties
v6: Review comments on formatting the table. [Laurent's review comments]
v7: Minor restructuring. [Laurent's review comments]
Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-03-11 19:55:29 +05:30
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2014-10-22 12:03:04 +10:00
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2014-10-20 16:30:50 +10:00
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2014-12-18 16:01:54 -05:00
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2014-12-18 16:01:53 -05:00
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2014-06-09 14:20:22 +01:00
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2014-12-18 16:01:53 -05:00
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|
Documentation: drm: describing drm properties exposed by various drivers
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du
v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]
v4: Removed whitespace warnings and minor nits. [Randy's review comments]
v5: Restructured output for ENUM properties
v6: Review comments on formatting the table. [Laurent's review comments]
v7: Minor restructuring. [Laurent's review comments]
Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-03-11 19:55:29 +05:30
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2014-11-10 10:18:15 +10:00
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2016-05-02 15:13:01 -04:00
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2014-06-11 14:33:05 +05:30
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2016-05-02 15:13:01 -04:00
|
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2014-06-11 14:33:05 +05:30
|
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|
Documentation: drm: describing drm properties exposed by various drivers
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du
v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]
v4: Removed whitespace warnings and minor nits. [Randy's review comments]
v5: Restructured output for ENUM properties
v6: Review comments on formatting the table. [Laurent's review comments]
v7: Minor restructuring. [Laurent's review comments]
Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-03-11 19:55:29 +05:30
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2016-02-26 17:05:00 +00:00
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2015-05-28 16:35:07 +05:30
|
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|
2014-07-08 10:32:02 +05:30
|
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|
|
Documentation: drm: describing drm properties exposed by various drivers
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du
v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]
v4: Removed whitespace warnings and minor nits. [Randy's review comments]
v5: Restructured output for ENUM properties
v6: Review comments on formatting the table. [Laurent's review comments]
v7: Minor restructuring. [Laurent's review comments]
Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-03-11 19:55:29 +05:30
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2016-03-16 10:57:16 +00:00
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Documentation: drm: describing drm properties exposed by various drivers
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du
v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]
v4: Removed whitespace warnings and minor nits. [Randy's review comments]
v5: Restructured output for ENUM properties
v6: Review comments on formatting the table. [Laurent's review comments]
v7: Minor restructuring. [Laurent's review comments]
Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-03-11 19:55:29 +05:30
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2014-07-08 10:32:02 +05:30
|
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|
Documentation: drm: describing drm properties exposed by various drivers
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du
v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]
v4: Removed whitespace warnings and minor nits. [Randy's review comments]
v5: Restructured output for ENUM properties
v6: Review comments on formatting the table. [Laurent's review comments]
v7: Minor restructuring. [Laurent's review comments]
Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-03-11 19:55:29 +05:30
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2014-07-08 10:32:02 +05:30
|
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|
Documentation: drm: describing drm properties exposed by various drivers
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du
v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]
v4: Removed whitespace warnings and minor nits. [Randy's review comments]
v5: Restructured output for ENUM properties
v6: Review comments on formatting the table. [Laurent's review comments]
v7: Minor restructuring. [Laurent's review comments]
Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-03-11 19:55:29 +05:30
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2014-07-08 10:32:02 +05:30
|
|
|
|
Documentation: drm: describing drm properties exposed by various drivers
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du
v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]
v4: Removed whitespace warnings and minor nits. [Randy's review comments]
v5: Restructured output for ENUM properties
v6: Review comments on formatting the table. [Laurent's review comments]
v7: Minor restructuring. [Laurent's review comments]
Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-03-11 19:55:29 +05:30
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2014-07-08 10:32:02 +05:30
|
|
|
|
Documentation: drm: describing drm properties exposed by various drivers
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du
v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]
v4: Removed whitespace warnings and minor nits. [Randy's review comments]
v5: Restructured output for ENUM properties
v6: Review comments on formatting the table. [Laurent's review comments]
v7: Minor restructuring. [Laurent's review comments]
Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-03-11 19:55:29 +05:30
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2014-07-08 10:32:02 +05:30
|
|
|
|
Documentation: drm: describing drm properties exposed by various drivers
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du
v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]
v4: Removed whitespace warnings and minor nits. [Randy's review comments]
v5: Restructured output for ENUM properties
v6: Review comments on formatting the table. [Laurent's review comments]
v7: Minor restructuring. [Laurent's review comments]
Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-03-11 19:55:29 +05:30
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2015-07-07 19:13:37 +01:00
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2015-05-28 16:35:07 +05:30
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|
Documentation: drm: describing drm properties exposed by various drivers
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du
v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]
v4: Removed whitespace warnings and minor nits. [Randy's review comments]
v5: Restructured output for ENUM properties
v6: Review comments on formatting the table. [Laurent's review comments]
v7: Minor restructuring. [Laurent's review comments]
Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-03-11 19:55:29 +05:30
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2014-07-08 10:32:02 +05:30
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|
|
Documentation: drm: describing drm properties exposed by various drivers
Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.
v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du
v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]
v4: Removed whitespace warnings and minor nits. [Randy's review comments]
v5: Restructured output for ENUM properties
v6: Review comments on formatting the table. [Laurent's review comments]
v7: Minor restructuring. [Laurent's review comments]
Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-03-11 19:55:29 +05:30
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2014-08-06 14:49:53 +03:00
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2014-08-06 14:49:54 +03:00
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2012-07-13 00:57:26 +02:00
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2014-05-08 16:41:51 +02:00
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2014-09-23 15:46:54 +02:00
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2014-05-08 16:41:51 +02:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2013-08-08 15:41:15 +02:00
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2009-10-26 13:06:31 -07:00
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2013-08-08 15:41:15 +02:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2013-08-08 15:41:15 +02:00
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2015-10-11 11:55:00 +02:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2016-01-11 22:40:55 +01:00
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2012-07-13 00:57:26 +02:00
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2015-09-28 21:42:40 +02:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2015-09-08 13:56:27 +02:00
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2009-10-26 13:06:31 -07:00
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2014-01-22 16:46:44 +01:00
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2009-10-26 13:06:31 -07:00
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2014-05-15 13:54:06 -07:00
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2014-01-22 16:46:44 +01:00
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2014-05-15 13:54:06 -07:00
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2014-01-22 16:46:44 +01:00
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2009-10-26 13:06:31 -07:00
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2014-01-22 16:46:44 +01:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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2009-10-26 13:06:31 -07:00
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2011-08-29 18:05:52 +00:00
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2011-08-29 18:07:13 +00:00
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2009-10-26 13:06:31 -07:00
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2011-08-29 19:29:16 +00:00
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2009-10-26 13:06:31 -07:00
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2012-07-13 00:57:26 +02:00
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|
drm: implement experimental render nodes
Render nodes provide an API for userspace to use non-privileged GPU
commands without any running DRM-Master. It is useful for offscreen
rendering, GPGPU clients, and normal render clients which do not perform
modesetting.
Compared to legacy clients, render clients no longer need any
authentication to perform client ioctls. Instead, user-space controls
render/client access to GPUs via filesystem access-modes on the
render-node. Once a render-node was opened, a client has full access to
the client/render operations on the GPU. However, no modesetting or ioctls
that affect global state are allowed on render nodes.
To prevent privilege-escalation, drivers must explicitly state that they
support render nodes. They must mark their render-only ioctls as
DRM_RENDER_ALLOW so render clients can use them. Furthermore, they must
support clients without any attached master.
If filesystem access-modes are not enough for fine-grained access control
to render nodes (very unlikely, considering the versaitlity of FS-ACLs),
you may still fall-back to fd-passing from server to client (which allows
arbitrary access-control). However, note that revoking access is
currently impossible and unlikely to get implemented.
Note: Render clients no longer have any associated DRM-Master as they are
supposed to be independent of any server state. DRM core highly depends on
file_priv->master to be non-NULL for modesetting/ctx/etc. commands.
Therefore, drivers must be very careful to not require DRM-Master if they
support DRIVER_RENDER.
So far render-nodes are protected by "drm_rnodes". As long as this
module-parameter is not set to 1, a driver will not create render nodes.
This allows us to experiment with the API a bit before we stabilize it.
v2: drop insecure GEM_FLINK to force use of dmabuf
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-08-25 18:29:00 +02:00
|
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|
|
2014-01-21 12:51:43 +01:00
|
|
|
|
|
|
|
|
|
drm: implement experimental render nodes
Render nodes provide an API for userspace to use non-privileged GPU
commands without any running DRM-Master. It is useful for offscreen
rendering, GPGPU clients, and normal render clients which do not perform
modesetting.
Compared to legacy clients, render clients no longer need any
authentication to perform client ioctls. Instead, user-space controls
render/client access to GPUs via filesystem access-modes on the
render-node. Once a render-node was opened, a client has full access to
the client/render operations on the GPU. However, no modesetting or ioctls
that affect global state are allowed on render nodes.
To prevent privilege-escalation, drivers must explicitly state that they
support render nodes. They must mark their render-only ioctls as
DRM_RENDER_ALLOW so render clients can use them. Furthermore, they must
support clients without any attached master.
If filesystem access-modes are not enough for fine-grained access control
to render nodes (very unlikely, considering the versaitlity of FS-ACLs),
you may still fall-back to fd-passing from server to client (which allows
arbitrary access-control). However, note that revoking access is
currently impossible and unlikely to get implemented.
Note: Render clients no longer have any associated DRM-Master as they are
supposed to be independent of any server state. DRM core highly depends on
file_priv->master to be non-NULL for modesetting/ctx/etc. commands.
Therefore, drivers must be very careful to not require DRM-Master if they
support DRIVER_RENDER.
So far render-nodes are protected by "drm_rnodes". As long as this
module-parameter is not set to 1, a driver will not create render nodes.
This allows us to experiment with the API a bit before we stabilize it.
v2: drop insecure GEM_FLINK to force use of dmabuf
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-08-25 18:29:00 +02:00
|
|
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|
2014-01-21 12:51:43 +01:00
|
|
|
|
drm: implement experimental render nodes
Render nodes provide an API for userspace to use non-privileged GPU
commands without any running DRM-Master. It is useful for offscreen
rendering, GPGPU clients, and normal render clients which do not perform
modesetting.
Compared to legacy clients, render clients no longer need any
authentication to perform client ioctls. Instead, user-space controls
render/client access to GPUs via filesystem access-modes on the
render-node. Once a render-node was opened, a client has full access to
the client/render operations on the GPU. However, no modesetting or ioctls
that affect global state are allowed on render nodes.
To prevent privilege-escalation, drivers must explicitly state that they
support render nodes. They must mark their render-only ioctls as
DRM_RENDER_ALLOW so render clients can use them. Furthermore, they must
support clients without any attached master.
If filesystem access-modes are not enough for fine-grained access control
to render nodes (very unlikely, considering the versaitlity of FS-ACLs),
you may still fall-back to fd-passing from server to client (which allows
arbitrary access-control). However, note that revoking access is
currently impossible and unlikely to get implemented.
Note: Render clients no longer have any associated DRM-Master as they are
supposed to be independent of any server state. DRM core highly depends on
file_priv->master to be non-NULL for modesetting/ctx/etc. commands.
Therefore, drivers must be very careful to not require DRM-Master if they
support DRIVER_RENDER.
So far render-nodes are protected by "drm_rnodes". As long as this
module-parameter is not set to 1, a driver will not create render nodes.
This allows us to experiment with the API a bit before we stabilize it.
v2: drop insecure GEM_FLINK to force use of dmabuf
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-08-25 18:29:00 +02:00
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
2014-01-21 12:51:43 +01:00
|
|
|
|
drm: implement experimental render nodes
Render nodes provide an API for userspace to use non-privileged GPU
commands without any running DRM-Master. It is useful for offscreen
rendering, GPGPU clients, and normal render clients which do not perform
modesetting.
Compared to legacy clients, render clients no longer need any
authentication to perform client ioctls. Instead, user-space controls
render/client access to GPUs via filesystem access-modes on the
render-node. Once a render-node was opened, a client has full access to
the client/render operations on the GPU. However, no modesetting or ioctls
that affect global state are allowed on render nodes.
To prevent privilege-escalation, drivers must explicitly state that they
support render nodes. They must mark their render-only ioctls as
DRM_RENDER_ALLOW so render clients can use them. Furthermore, they must
support clients without any attached master.
If filesystem access-modes are not enough for fine-grained access control
to render nodes (very unlikely, considering the versaitlity of FS-ACLs),
you may still fall-back to fd-passing from server to client (which allows
arbitrary access-control). However, note that revoking access is
currently impossible and unlikely to get implemented.
Note: Render clients no longer have any associated DRM-Master as they are
supposed to be independent of any server state. DRM core highly depends on
file_priv->master to be non-NULL for modesetting/ctx/etc. commands.
Therefore, drivers must be very careful to not require DRM-Master if they
support DRIVER_RENDER.
So far render-nodes are protected by "drm_rnodes". As long as this
module-parameter is not set to 1, a driver will not create render nodes.
This allows us to experiment with the API a bit before we stabilize it.
v2: drop insecure GEM_FLINK to force use of dmabuf
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-08-25 18:29:00 +02:00
|
|
|
|
2014-01-21 12:51:43 +01:00
|
|
|
|
drm: implement experimental render nodes
Render nodes provide an API for userspace to use non-privileged GPU
commands without any running DRM-Master. It is useful for offscreen
rendering, GPGPU clients, and normal render clients which do not perform
modesetting.
Compared to legacy clients, render clients no longer need any
authentication to perform client ioctls. Instead, user-space controls
render/client access to GPUs via filesystem access-modes on the
render-node. Once a render-node was opened, a client has full access to
the client/render operations on the GPU. However, no modesetting or ioctls
that affect global state are allowed on render nodes.
To prevent privilege-escalation, drivers must explicitly state that they
support render nodes. They must mark their render-only ioctls as
DRM_RENDER_ALLOW so render clients can use them. Furthermore, they must
support clients without any attached master.
If filesystem access-modes are not enough for fine-grained access control
to render nodes (very unlikely, considering the versaitlity of FS-ACLs),
you may still fall-back to fd-passing from server to client (which allows
arbitrary access-control). However, note that revoking access is
currently impossible and unlikely to get implemented.
Note: Render clients no longer have any associated DRM-Master as they are
supposed to be independent of any server state. DRM core highly depends on
file_priv->master to be non-NULL for modesetting/ctx/etc. commands.
Therefore, drivers must be very careful to not require DRM-Master if they
support DRIVER_RENDER.
So far render-nodes are protected by "drm_rnodes". As long as this
module-parameter is not set to 1, a driver will not create render nodes.
This allows us to experiment with the API a bit before we stabilize it.
v2: drop insecure GEM_FLINK to force use of dmabuf
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-08-25 18:29:00 +02:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2014-01-21 12:51:43 +01:00
|
|
|
|
drm: implement experimental render nodes
Render nodes provide an API for userspace to use non-privileged GPU
commands without any running DRM-Master. It is useful for offscreen
rendering, GPGPU clients, and normal render clients which do not perform
modesetting.
Compared to legacy clients, render clients no longer need any
authentication to perform client ioctls. Instead, user-space controls
render/client access to GPUs via filesystem access-modes on the
render-node. Once a render-node was opened, a client has full access to
the client/render operations on the GPU. However, no modesetting or ioctls
that affect global state are allowed on render nodes.
To prevent privilege-escalation, drivers must explicitly state that they
support render nodes. They must mark their render-only ioctls as
DRM_RENDER_ALLOW so render clients can use them. Furthermore, they must
support clients without any attached master.
If filesystem access-modes are not enough for fine-grained access control
to render nodes (very unlikely, considering the versaitlity of FS-ACLs),
you may still fall-back to fd-passing from server to client (which allows
arbitrary access-control). However, note that revoking access is
currently impossible and unlikely to get implemented.
Note: Render clients no longer have any associated DRM-Master as they are
supposed to be independent of any server state. DRM core highly depends on
file_priv->master to be non-NULL for modesetting/ctx/etc. commands.
Therefore, drivers must be very careful to not require DRM-Master if they
support DRIVER_RENDER.
So far render-nodes are protected by "drm_rnodes". As long as this
module-parameter is not set to 1, a driver will not create render nodes.
This allows us to experiment with the API a bit before we stabilize it.
v2: drop insecure GEM_FLINK to force use of dmabuf
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-08-25 18:29:00 +02:00
|
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|
2012-07-13 00:57:26 +02:00
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|
2014-05-08 15:39:19 +02:00
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|
2012-07-13 00:57:26 +02:00
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|
2009-10-26 13:06:31 -07:00
|
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|
2014-01-22 12:21:16 +01:00
|
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|
|
2009-10-26 13:06:31 -07:00
|
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|
|
2014-01-22 12:21:16 +01:00
|
|
|
|
|
|
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|
|
2015-10-11 11:26:26 +02:00
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|
2014-01-22 12:21:16 +01:00
|
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2009-10-26 13:06:31 -07:00
|
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|
2014-01-22 12:21:16 +01:00
|
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|
2009-10-26 13:06:31 -07:00
|
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2014-01-22 12:21:16 +01:00
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|
2009-10-26 13:06:31 -07:00
|
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|
2014-09-30 10:56:42 +02:00
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2015-01-28 17:47:58 +02:00
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|
2014-09-30 10:56:42 +02:00
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2014-09-30 10:56:45 +02:00
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2015-02-10 19:05:47 +08:00
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2014-09-30 10:56:42 +02:00
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2014-01-22 12:21:16 +01:00
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2014-09-19 18:27:27 +02:00
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2014-09-30 10:56:50 +02:00
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2014-09-19 18:27:27 +02:00
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2014-01-22 12:21:16 +01:00
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2014-12-23 10:41:52 -08:00
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2014-01-22 12:21:16 +01:00
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2015-07-02 16:05:28 +03:00
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2014-10-27 16:27:00 +02:00
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2015-10-01 17:01:09 +08:00
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2014-11-14 08:52:29 -08:00
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2014-12-08 06:46:31 -08:00
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2015-02-13 15:33:03 +05:30
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2014-10-27 16:27:00 +02:00
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2014-04-25 20:14:31 +03:00
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2015-05-13 22:13:29 +05:30
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2015-12-21 15:10:52 +02:00
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2016-03-16 12:43:35 +02:00
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2015-12-21 15:10:52 +02:00
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2014-01-22 12:21:16 +01:00
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2009-10-26 13:06:31 -07:00
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2014-01-22 12:21:16 +01:00
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2014-04-25 16:59:00 +02:00
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2014-12-11 12:13:08 -08:00
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2014-04-25 16:59:00 +02:00
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2014-07-24 17:04:48 +01:00
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2014-12-10 17:27:59 +00:00
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2015-07-24 17:40:12 +02:00
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2015-07-24 17:40:15 +02:00
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2015-07-24 17:40:12 +02:00
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2015-07-24 17:40:15 +02:00
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2014-12-10 17:27:59 +00:00
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2015-01-05 14:36:59 +01:00
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2015-03-18 14:47:59 +01:00
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2015-01-05 14:36:59 +01:00
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2015-03-18 14:47:59 +01:00
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2014-01-22 12:21:16 +01:00
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drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 15:43:43 +01:00
|
|
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2015-10-19 16:10:54 -07:00
|
|
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|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 15:43:43 +01:00
|
|
|
|
2015-10-19 16:10:54 -07:00
|
|
|
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 15:43:43 +01:00
|
|
|
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|
|
2015-10-19 16:10:54 -07:00
|
|
|
|
|
|
|
|
|
2015-08-24 14:41:21 +01:00
|
|
|
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 15:43:43 +01:00
|
|
|
|
2015-10-19 16:10:54 -07:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 15:43:43 +01:00
|
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|
|
2014-11-10 13:44:31 +00:00
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2014-01-22 12:21:16 +01:00
|
|
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|
2014-09-30 10:56:45 +02:00
|
|
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|
2014-01-22 12:21:16 +01:00
|
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2015-10-11 11:55:00 +02:00
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2016-01-02 18:47:17 +01:00
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2015-10-11 11:55:00 +02:00
|
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2016-01-02 18:47:17 +01:00
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2015-10-11 11:55:00 +02:00
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2016-01-02 18:47:17 +01:00
|
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2015-10-11 11:55:00 +02:00
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2016-01-02 18:47:17 +01:00
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2015-10-11 11:55:00 +02:00
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2016-01-02 18:47:17 +01:00
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2015-10-11 11:55:00 +02:00
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2016-01-02 18:47:17 +01:00
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2016-01-11 20:09:20 +01:00
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2015-10-11 11:55:00 +02:00
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2016-01-02 18:47:17 +01:00
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2015-10-11 11:55:00 +02:00
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2016-01-02 18:47:17 +01:00
|
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2015-10-11 11:55:00 +02:00
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|
apple-gmux: Add initial documentation
Document what I've learned so far about the gmux so that we can
collaboratively reverse-engineer its remaining unknown bits
without everyone having to start from scratch.
The DOC sections are bound together in the gpu.tmpl DocBook
under a new vga_switcheroo "Handlers" chapter. Eventually
this should be amended with documentation about the four other
handlers that exist so far (nouveau v1 DSM, nouveau Optimus DSM,
radeon ATPX, amdgpu ATPX).
Requires kernel-doc with asciidoc support.
The EFI variable was reverse-engineered by Bruno Bierbaumer
<bruno@bierbaumer.net> and Andreas Heider <andreas@meetr.de>.
Some of the remaining open questions:
* How are vblank intervals synchronized on retinas to achieve seamless
switching? Is the DP mux capable of this? It's not mentioned in the
data sheets. Or is it done at the OS level, i.e. do we have to
synchronize vblank intervals between DRM drivers? There's a signal
coming from the panel connector and going into gmux, could this be
the vblank signal as received by the panel to properly time the
switch?
* On retinas there's an I2C bus between gmux and the connector of the
right I/O board, apparently leading to the Parade PS8401A HDMI
repeater. What is this for, is it controlled via gmux registers?
Data sheet:
http://www.paradetech.com/products/jitter-cleaning-repeaters/ps8401/
* On retinas there's an I2C bus between gmux and the LED driver.
Pre-retinas connected the LED driver to SMBUS. Are there additional
gmux registers on retinas to control it?
* The MacPro6,1 2013 also has a gmux, the same Renesas R4F2113 as the
retina MacBook Pro. The Mac Pro doesn't have a built-in display,
so what is its purpose? Power control of the dual FirePro GPUs?
Switching of the external DP/Thunderbolt ports? The iFixit teardown
clearly shows one TI HD3SS212 DisplayPort mux on the logic board next
to one of the three Thunderbolt controllers. However six muxes would
be necessary to switch all six ports between GPUs. The mux is probably
necessary for one of the display configurations allowed by Apple,
but which one?
https://www.ifixit.com/Teardown/Mac+Pro+Late+2013+Teardown/20778
https://d3nevzfk7ii3be.cloudfront.net/igi/fELBTnt31QhnDsqq.huge
https://support.apple.com/en-us/HT202801
* Registers we haven't decoded yet:
0x700 32 Bit configmap?
0x708 32 Bit power sequence?
0x712 8 Bit status of clock from panel on retinas?
0x713 8 Bit dito?
0x724 16 Bit backlight, raw value?
0x760 32 Bit backlight
0x764 32 Bit backlight
0x768 8 Bit backlight
0x76a 16 Bit backlight
0x76c 16 Bit backlight
0x76e 16 Bit backlight
0x77f edp/dp/hdmi probe? retina only.
* Addition by Bruno Prémont <bonbons@linux-vserver.org>:
"Missing is also precise knowledge as to what the gmux depends on.
From behavioral reports, it is somehow sensitive to VGA IO/MEM
routing (it apparently needs the routing to go to integrated GPU,
not discrete GPU).
When the routing is inappropriate backlight control IO just reads back
as 0xFF (and eventually gmux IO in general does so)."
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Acked-by: Darren Hart <dvhart@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/da309e436fbeac886477d80376457b7d83ea4b2d.1452431795.git.lukas@wunner.de
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-01-11 00:08:35 +01:00
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2016-01-11 20:09:20 +01:00
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|
apple-gmux: Add initial documentation
Document what I've learned so far about the gmux so that we can
collaboratively reverse-engineer its remaining unknown bits
without everyone having to start from scratch.
The DOC sections are bound together in the gpu.tmpl DocBook
under a new vga_switcheroo "Handlers" chapter. Eventually
this should be amended with documentation about the four other
handlers that exist so far (nouveau v1 DSM, nouveau Optimus DSM,
radeon ATPX, amdgpu ATPX).
Requires kernel-doc with asciidoc support.
The EFI variable was reverse-engineered by Bruno Bierbaumer
<bruno@bierbaumer.net> and Andreas Heider <andreas@meetr.de>.
Some of the remaining open questions:
* How are vblank intervals synchronized on retinas to achieve seamless
switching? Is the DP mux capable of this? It's not mentioned in the
data sheets. Or is it done at the OS level, i.e. do we have to
synchronize vblank intervals between DRM drivers? There's a signal
coming from the panel connector and going into gmux, could this be
the vblank signal as received by the panel to properly time the
switch?
* On retinas there's an I2C bus between gmux and the connector of the
right I/O board, apparently leading to the Parade PS8401A HDMI
repeater. What is this for, is it controlled via gmux registers?
Data sheet:
http://www.paradetech.com/products/jitter-cleaning-repeaters/ps8401/
* On retinas there's an I2C bus between gmux and the LED driver.
Pre-retinas connected the LED driver to SMBUS. Are there additional
gmux registers on retinas to control it?
* The MacPro6,1 2013 also has a gmux, the same Renesas R4F2113 as the
retina MacBook Pro. The Mac Pro doesn't have a built-in display,
so what is its purpose? Power control of the dual FirePro GPUs?
Switching of the external DP/Thunderbolt ports? The iFixit teardown
clearly shows one TI HD3SS212 DisplayPort mux on the logic board next
to one of the three Thunderbolt controllers. However six muxes would
be necessary to switch all six ports between GPUs. The mux is probably
necessary for one of the display configurations allowed by Apple,
but which one?
https://www.ifixit.com/Teardown/Mac+Pro+Late+2013+Teardown/20778
https://d3nevzfk7ii3be.cloudfront.net/igi/fELBTnt31QhnDsqq.huge
https://support.apple.com/en-us/HT202801
* Registers we haven't decoded yet:
0x700 32 Bit configmap?
0x708 32 Bit power sequence?
0x712 8 Bit status of clock from panel on retinas?
0x713 8 Bit dito?
0x724 16 Bit backlight, raw value?
0x760 32 Bit backlight
0x764 32 Bit backlight
0x768 8 Bit backlight
0x76a 16 Bit backlight
0x76c 16 Bit backlight
0x76e 16 Bit backlight
0x77f edp/dp/hdmi probe? retina only.
* Addition by Bruno Prémont <bonbons@linux-vserver.org>:
"Missing is also precise knowledge as to what the gmux depends on.
From behavioral reports, it is somehow sensitive to VGA IO/MEM
routing (it apparently needs the routing to go to integrated GPU,
not discrete GPU).
When the routing is inappropriate backlight control IO just reads back
as 0xFF (and eventually gmux IO in general does so)."
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Acked-by: Darren Hart <dvhart@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/da309e436fbeac886477d80376457b7d83ea4b2d.1452431795.git.lukas@wunner.de
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-01-11 00:08:35 +01:00
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2015-10-11 11:55:00 +02:00
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apple-gmux: Add initial documentation
Document what I've learned so far about the gmux so that we can
collaboratively reverse-engineer its remaining unknown bits
without everyone having to start from scratch.
The DOC sections are bound together in the gpu.tmpl DocBook
under a new vga_switcheroo "Handlers" chapter. Eventually
this should be amended with documentation about the four other
handlers that exist so far (nouveau v1 DSM, nouveau Optimus DSM,
radeon ATPX, amdgpu ATPX).
Requires kernel-doc with asciidoc support.
The EFI variable was reverse-engineered by Bruno Bierbaumer
<bruno@bierbaumer.net> and Andreas Heider <andreas@meetr.de>.
Some of the remaining open questions:
* How are vblank intervals synchronized on retinas to achieve seamless
switching? Is the DP mux capable of this? It's not mentioned in the
data sheets. Or is it done at the OS level, i.e. do we have to
synchronize vblank intervals between DRM drivers? There's a signal
coming from the panel connector and going into gmux, could this be
the vblank signal as received by the panel to properly time the
switch?
* On retinas there's an I2C bus between gmux and the connector of the
right I/O board, apparently leading to the Parade PS8401A HDMI
repeater. What is this for, is it controlled via gmux registers?
Data sheet:
http://www.paradetech.com/products/jitter-cleaning-repeaters/ps8401/
* On retinas there's an I2C bus between gmux and the LED driver.
Pre-retinas connected the LED driver to SMBUS. Are there additional
gmux registers on retinas to control it?
* The MacPro6,1 2013 also has a gmux, the same Renesas R4F2113 as the
retina MacBook Pro. The Mac Pro doesn't have a built-in display,
so what is its purpose? Power control of the dual FirePro GPUs?
Switching of the external DP/Thunderbolt ports? The iFixit teardown
clearly shows one TI HD3SS212 DisplayPort mux on the logic board next
to one of the three Thunderbolt controllers. However six muxes would
be necessary to switch all six ports between GPUs. The mux is probably
necessary for one of the display configurations allowed by Apple,
but which one?
https://www.ifixit.com/Teardown/Mac+Pro+Late+2013+Teardown/20778
https://d3nevzfk7ii3be.cloudfront.net/igi/fELBTnt31QhnDsqq.huge
https://support.apple.com/en-us/HT202801
* Registers we haven't decoded yet:
0x700 32 Bit configmap?
0x708 32 Bit power sequence?
0x712 8 Bit status of clock from panel on retinas?
0x713 8 Bit dito?
0x724 16 Bit backlight, raw value?
0x760 32 Bit backlight
0x764 32 Bit backlight
0x768 8 Bit backlight
0x76a 16 Bit backlight
0x76c 16 Bit backlight
0x76e 16 Bit backlight
0x77f edp/dp/hdmi probe? retina only.
* Addition by Bruno Prémont <bonbons@linux-vserver.org>:
"Missing is also precise knowledge as to what the gmux depends on.
From behavioral reports, it is somehow sensitive to VGA IO/MEM
routing (it apparently needs the routing to go to integrated GPU,
not discrete GPU).
When the routing is inappropriate backlight control IO just reads back
as 0xFF (and eventually gmux IO in general does so)."
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Acked-by: Darren Hart <dvhart@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/da309e436fbeac886477d80376457b7d83ea4b2d.1452431795.git.lukas@wunner.de
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-01-11 00:08:35 +01:00
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2015-10-11 11:55:00 +02:00
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2009-10-26 13:06:31 -07:00
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