2019-06-04 10:11:33 +02:00
|
|
|
|
2013-01-18 15:12:20 +05:30
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2019-10-23 15:44:15 +03:00
|
|
|
|
2013-01-18 15:12:20 +05:30
|
|
|
|
2019-06-03 09:31:19 +03:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2018-06-01 14:34:33 +03:00
|
|
|
|
2015-06-28 20:22:01 +05:30
|
|
|
|
ARCv2: build: use mcpu=hs38 iso generic mcpu=archs
helps gcc with better instruction selections such as 64-bit multiply MPYD
before
------
82c34b58 <sched_clock>:
82c34b58: ld r2,[0x83068d00]
82c34b60: add_s r2,r2,0x7530
82c34b66: mov_s r0,0x989680
82c34b6c: mpymu r5,r2,r0
82c34b70: mpy r4,r2,r0
82c34b74: mov_s r0,r4
82c34b76: j_s.d [blink]
82c34b78: mov_s r1,r5
82c34b7a: nop_s
after
------
82c34b7c <sched_clock>:
82c34b7c: ld r0,[0x83064d00]
82c34b84: add_s r0,r0,0x7530
82c34b8a: mpydu r0,r0,0x989680
82c34b92: j_s [blink]
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2018-09-07 15:13:10 -07:00
|
|
|
|
2013-01-18 15:12:20 +05:30
|
|
|
|
2013-02-11 19:52:57 +05:30
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2013-06-01 12:55:42 +05:30
|
|
|
|
2013-02-11 19:52:57 +05:30
|
|
|
|
2019-07-06 12:07:11 +09:00
|
|
|
|
2013-02-11 19:52:57 +05:30
|
|
|
|
|
|
|
|
|
2018-08-27 12:07:37 +09:00
|
|
|
|
2013-01-18 15:12:20 +05:30
|
|
|
|
2016-11-08 08:47:14 -08:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2015-07-16 21:45:38 +03:00
|
|
|
|
|
|
|
|
|
2019-01-30 19:32:41 +03:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
2015-07-16 21:45:38 +03:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 18:30:41 +05:30
|
|
|
|
|
|
|
|
|
2016-09-16 17:23:26 -07:00
|
|
|
|
|
|
|
|
|
2013-06-24 21:22:06 +05:30
|
|
|
|
2013-01-18 15:12:20 +05:30
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2018-09-16 23:47:57 +03:00
|
|
|
|
2013-01-18 15:12:20 +05:30
|
|
|
|
|
|
|
|
|
2015-12-21 12:38:01 +05:30
|
|
|
|
2013-01-18 15:12:20 +05:30
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2018-08-24 08:20:39 +09:00
|
|
|
|
2013-01-18 15:12:20 +05:30
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2013-01-22 17:00:52 +05:30
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2017-07-28 16:53:50 +05:30
|
|
|
|
2015-02-20 19:12:18 +05:30
|
|
|
|
2014-01-27 14:51:34 +01:00
|
|
|
|
2015-10-16 16:52:43 +03:00
|
|
|
|
2017-08-15 21:13:55 +03:00
|
|
|
|
2015-10-16 16:52:43 +03:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2013-01-18 15:12:20 +05:30
|
|
|
|
2013-01-22 17:02:38 +05:30
|
|
|
|
|
|
|
|
|
2013-01-18 15:12:20 +05:30
|
|
|
|
|
|
|
|
|
2013-03-22 19:48:01 +05:30
|
|
|
|
|
|
|
|
|
2016-05-21 13:45:35 +02:00
|
|
|
|
2016-11-22 22:34:31 +01:00
|
|
|
|
2013-01-18 15:12:20 +05:30
|
|
|
|
2016-11-22 22:34:31 +01:00
|
|
|
|
2013-01-18 15:12:20 +05:30
|
|
|
|
|
|
|
|
|
2013-03-22 22:04:27 +05:30
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2013-01-18 15:12:20 +05:30
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|