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treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-19 13:07:45 +01:00
[I/OAT]: DMA memcpy subsystem Provides an API for offloading memory copies to DMA devices Signed-off-by: Chris Leech <christopher.leech@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-05-23 17:18:44 -07:00
I/OAT: Add DCA services Add code to connect to the DCA driver and provide cpu tags for use by drivers that would like to use Direct Cache Access hints. [Adrian Bunk] Several Kconfig cleanup items [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when built for uni-processor Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 01:27:42 -07:00
dmaengine: correct invalid assumptions in the Kconfig text This patch corrects recently changed (and now invalid) Kconfig descriptions for the DMA engine framework: - Non-Intel(R) hardware also has DMA engines; - DMA is used for more than memcpy and RAID offloading. In fact, on most platforms memcpy and RAID aren't factors, and DMA exists so that peripherals can transfer data to/from memory while the CPU does other work. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-11-28 16:21:43 -08:00
async_xor: permit callers to pass in a 'dma/page scribble' region async_xor() needs space to perform dma and page address conversions. In most cases the code can simply reuse the struct page * array because the size of the native pointer matches the size of a dma/page address. In order to support archs where sizeof(dma_addr_t) is larger than sizeof(struct page *), or to preserve the input parameters, we utilize a memory region passed in by the caller. Since the code is now prepared to handle the case where it cannot perform address conversions on the stack, we no longer need the !HIGHMEM64G dependency in drivers/dma/Kconfig. [ Impact: don't clobber input buffers for address conversions ] Reviewed-by: Andre Noll <maan@systemlinux.org> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-06-03 14:22:28 -07:00
I/OAT: Add DCA services Add code to connect to the DCA driver and provide cpu tags for use by drivers that would like to use Direct Cache Access hints. [Adrian Bunk] Several Kconfig cleanup items [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when built for uni-processor Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 01:27:42 -07:00
dmaengine: correct invalid assumptions in the Kconfig text This patch corrects recently changed (and now invalid) Kconfig descriptions for the DMA engine framework: - Non-Intel(R) hardware also has DMA engines; - DMA is used for more than memcpy and RAID offloading. In fact, on most platforms memcpy and RAID aren't factors, and DMA exists so that peripherals can transfer data to/from memory while the CPU does other work. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-11-28 16:21:43 -08:00
dmaengine: remove arch dependency from DMADEVICES The dependency is redundant since all drivers set their specific arch dependencies. The NET_DMA option is modified to be enabled only on platforms where it is known to have a positive effect. HAS_DMA is added as an explicit dependency for the DMADEVICES menu. Acked-by: Adrian Bunk <bunk@kernel.org> Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-06-27 01:21:11 -07:00
I/OAT: Add DCA services Add code to connect to the DCA driver and provide cpu tags for use by drivers that would like to use Direct Cache Access hints. [Adrian Bunk] Several Kconfig cleanup items [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when built for uni-processor Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 01:27:42 -07:00
Debugging options for the DMA engine subsystem This adds Kconfig options for DEBUG and VERBOSE_DEBUG to the DMA engine subsystem, I got tired of editing the Makefile manually each time I want to debug things in here, modelled this on the debug switches for other subsystems and works like a charm when working on our DMA engines. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-02-09 22:34:54 +01:00
dmaengine: Fix Kconfig indentation Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^ /\t/' -i */Kconfig Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/1574306348-29212-1-git-send-email-krzk@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-11-21 04:19:08 +01:00
Debugging options for the DMA engine subsystem This adds Kconfig options for DEBUG and VERBOSE_DEBUG to the DMA engine subsystem, I got tired of editing the Makefile manually each time I want to debug things in here, modelled this on the debug switches for other subsystems and works like a charm when working on our DMA engines. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-02-09 22:34:54 +01:00
dmaengine: Fix Kconfig indentation Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^ /\t/' -i */Kconfig Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/1574306348-29212-1-git-send-email-krzk@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-11-21 04:19:08 +01:00
Debugging options for the DMA engine subsystem This adds Kconfig options for DEBUG and VERBOSE_DEBUG to the DMA engine subsystem, I got tired of editing the Makefile manually each time I want to debug things in here, modelled this on the debug switches for other subsystems and works like a charm when working on our DMA engines. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-02-09 22:34:54 +01:00
I/OAT: Add DCA services Add code to connect to the DCA driver and provide cpu tags for use by drivers that would like to use Direct Cache Access hints. [Adrian Bunk] Several Kconfig cleanup items [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when built for uni-processor Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 01:27:42 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dma: MIC X100 DMA Driver This patch implements DMA Engine API for DMA controller on MIC X100 Coprocessors. DMA h/w is shared between host and card s/w. Channels 0 to 3 are used by host and 4 to 7 are used by card. Since the DMA device doesn't show up as PCIe device, a virtual bus called mic bus is created and virtual devices are added on that bus to follow device model. Allowed dma transfer directions are host to card, card to host and card to card. Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Nikhil Rao <nikhil.rao@intel.com> Reviewed-by: Sudeep Dutt <sudeep.dutt@intel.com> Signed-off-by: Siva Yerramreddy <yshivakrishna@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-07-11 14:04:21 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dma: MIC X100 DMA Driver This patch implements DMA Engine API for DMA controller on MIC X100 Coprocessors. DMA h/w is shared between host and card s/w. Channels 0 to 3 are used by host and 4 to 7 are used by card. Since the DMA device doesn't show up as PCIe device, a virtual bus called mic bus is created and virtual devices are added on that bus to follow device model. Allowed dma transfer directions are host to card, card to host and card to card. Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Nikhil Rao <nikhil.rao@intel.com> Reviewed-by: Sudeep Dutt <sudeep.dutt@intel.com> Signed-off-by: Siva Yerramreddy <yshivakrishna@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-07-11 14:04:21 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine, async_tx: add a "no channel switch" allocator Channel switching is problematic for some dmaengine drivers as the architecture precludes separating the ->prep from ->submit. In these cases the driver can select ASYNC_TX_DISABLE_CHANNEL_SWITCH to modify the async_tx allocator to only return channels that support all of the required asynchronous operations. For example MD_RAID456=y selects support for asynchronous xor, xor validate, pq, pq validate, and memcpy. When ASYNC_TX_DISABLE_CHANNEL_SWITCH=y any channel with all these capabilities is marked DMA_ASYNC_TX allowing async_tx_find_channel() to quickly locate compatible channels with the guarantee that dependency chains will remain on one channel. When ASYNC_TX_DISABLE_CHANNEL_SWITCH=n async_tx_find_channel() may select channels that lead to operation chains that need to cross channel boundaries using the async_tx channel switch capability. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-09-08 17:42:51 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: Add driver for Altera / Intel mSGDMA IP core This driver adds support for the Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) intellectual property (IP) to the Linux DMAengine subsystem. Currently it supports the following op modes: - DMA_MEMCPY - DMA_SG - DMA_SLAVE This implementation has been tested on an Altera Cyclone FPGA connected via PCIe, both on an ARM and an x86 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-07 14:11:19 +02:00
dmaengine: driver for the ARM PL080/PL081 PrimeCells v5 This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells based on the implementation earlier submitted by Peter Pearse. This is working like a charm for memcpy and slave DMA to the PL011 PrimeCell on the PB11MPCore. This DMA controller is used in mostly unmodified form in the ARM RealView and Versatile platforms, in the ST-Ericsson Nomadik, and in the ST SPEAr platform. It has been converted to use the header from the Samsung PL080 derivate instead of its own defintions. The Samsungs have a custom driver in their mach-* folders though, atleast we can share the register definitions. Cc: Peter Pearse <peter.pearse@arm.com> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Alessandro Rubini <rubini@unipv.it> Acked-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> [GFP_KERNEL to GFP_NOWAIT in pl08x_prep_dma_memcpy] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-09-28 15:57:37 +02:00
drivers/dma: remove CONFIG_EXPERIMENTAL This config item has not carried much meaning for a while now and is almost always enabled by default. As agreed during the Linux kernel summit, remove it. CC: Vinod Koul <vinod.koul@intel.com> CC: Dan Williams <djbw@fb.com> Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2012-10-23 13:01:54 -07:00
dmaengine: driver for the ARM PL080/PL081 PrimeCells v5 This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells based on the implementation earlier submitted by Peter Pearse. This is working like a charm for memcpy and slave DMA to the PL011 PrimeCell on the PB11MPCore. This DMA controller is used in mostly unmodified form in the ARM RealView and Versatile platforms, in the ST-Ericsson Nomadik, and in the ST SPEAr platform. It has been converted to use the header from the Samsung PL080 derivate instead of its own defintions. The Samsungs have a custom driver in their mach-* folders though, atleast we can share the register definitions. Cc: Peter Pearse <peter.pearse@arm.com> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Alessandro Rubini <rubini@unipv.it> Acked-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> [GFP_KERNEL to GFP_NOWAIT in pl08x_prep_dma_memcpy] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-09-28 15:57:37 +02:00
dmaengine: PL08x: use vchan's spinlock Initialize the vchan struct, and use the provided spinlock rather than our own. Acked-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-05-26 14:09:53 +01:00
dmaengine: driver for the ARM PL080/PL081 PrimeCells v5 This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells based on the implementation earlier submitted by Peter Pearse. This is working like a charm for memcpy and slave DMA to the PL011 PrimeCell on the PB11MPCore. This DMA controller is used in mostly unmodified form in the ARM RealView and Versatile platforms, in the ST-Ericsson Nomadik, and in the ST SPEAr platform. It has been converted to use the header from the Samsung PL080 derivate instead of its own defintions. The Samsungs have a custom driver in their mach-* folders though, atleast we can share the register definitions. Cc: Peter Pearse <peter.pearse@arm.com> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Alessandro Rubini <rubini@unipv.it> Acked-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> [GFP_KERNEL to GFP_NOWAIT in pl08x_prep_dma_memcpy] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-09-28 15:57:37 +02:00
dmaengine: pl08x: Add support for Faraday Technology FTDMAC020 After reading the specs for the Faraday Technology FTDMAC020 found in the Gemini platform, it becomes pretty evident that this is just another PL08x derivative, and should be handled like such by simply extending the existing PL08x driver to handle the quirks in this hardware. This patch makes memcpy work and has been tested on the Gemini and also regression-tested on the Nomadik NHK15 using dmatest with 10 threads per channel without a hinch for hours. I have not implemented slave DMA in those codepaths, because this device (Gemini) does not use slave DMA, and it seems like devices using FTDMAC020 for device DMA have a slightly different register layout so some real hardware is needed to proceed with this. I left some FIXME etc in the code for this. I had to do some refactorings of some helper functions, but I have not split those into separate patches because these refactorings do not make much sense without the increased complexity of handling the FTDMAC020. The DMA test would hang the platform on me on the Gemini after a few thousand iterations, however after turning of the caches the problem immediately disappeared and I could run the DMA engine with 10 threads pers physical channel for days in a row without a crash. I think there is no problem with the DMA driver: instead it is something fishy in the FA526 cache handling code that get pretty heavily exercised by the DMA engine and we need to go and fix that instead. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-05-20 23:42:53 +02:00
dmaengine: driver for the ARM PL080/PL081 PrimeCells v5 This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells based on the implementation earlier submitted by Peter Pearse. This is working like a charm for memcpy and slave DMA to the PL011 PrimeCell on the PB11MPCore. This DMA controller is used in mostly unmodified form in the ARM RealView and Versatile platforms, in the ST-Ericsson Nomadik, and in the ST SPEAr platform. It has been converted to use the header from the Samsung PL080 derivate instead of its own defintions. The Samsungs have a custom driver in their mach-* folders though, atleast we can share the register definitions. Cc: Peter Pearse <peter.pearse@arm.com> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Alessandro Rubini <rubini@unipv.it> Acked-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> [GFP_KERNEL to GFP_NOWAIT in pl08x_prep_dma_memcpy] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-09-28 15:57:37 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
I/OAT: Add DCA services Add code to connect to the DCA driver and provide cpu tags for use by drivers that would like to use Direct Cache Access hints. [Adrian Bunk] Several Kconfig cleanup items [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when built for uni-processor Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 01:27:42 -07:00
dmaengine: fix enable for high order unmap pools The higher order mempools support raid operations, and we want to disable them when raid support is not enabled. Making them conditional on ASYNC_TX_DMA is not sufficient as other users (specifically dmatest) will also issue raid operations. Make raid drivers explicitly request that the core carry the higher order pools. Reported-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2013-12-09 10:33:16 -08:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
async_tx: make async_tx channel switching opt-in The majority of drivers in drivers/dma/ will never establish cross channel operation chains and do not need the extra overhead in struct dma_async_tx_descriptor. Make channel switching opt-in by default. Cc: Anatolij Gustschin <agust@denx.de> Cc: Ira Snyder <iws@ovro.caltech.edu> Cc: Linus Walleij <linus.walleij@stericsson.com> Cc: Saeed Bishara <saeed@marvell.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-10-07 16:44:50 -07:00
I/OAT: Add DCA services Add code to connect to the DCA driver and provide cpu tags for use by drivers that would like to use Direct Cache Access hints. [Adrian Bunk] Several Kconfig cleanup items [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when built for uni-processor Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 01:27:42 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
I/OAT: Add DCA services Add code to connect to the DCA driver and provide cpu tags for use by drivers that would like to use Direct Cache Access hints. [Adrian Bunk] Several Kconfig cleanup items [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when built for uni-processor Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 01:27:42 -07:00
dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller This AHB DMA Controller (aka HDMA or DMAC on AT91 systems) is availlable on at91sam9rl chip. It will be used on other products in the future. This first release covers only the memory-to-memory tranfer type. This is the only tranfer type supported by this chip. On other products, it will be used also for peripheral DMA transfer (slave API support to come). I used dmatest client without problem in different configurations to test it. Full documentation for this controller can be found in the SAM9RL datasheet: http://www.atmel.com/dyn/products/product_card.asp?part_id=4243 Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-03 19:24:33 +02:00
dmaengine: Kconfig: fix Atmel at_hdmac entry Remove SoC dependency and make it generic for every Atmel ARM AT91. That will allow to select this driver for newer chips. Keep dependency on AT91 because of the use of an header file located in include/mach directory. Modify the comment to reflect this. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
2012-03-15 11:31:58 +01:00
dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller This AHB DMA Controller (aka HDMA or DMAC on AT91 systems) is availlable on at91sam9rl chip. It will be used on other products in the future. This first release covers only the memory-to-memory tranfer type. This is the only tranfer type supported by this chip. On other products, it will be used also for peripheral DMA transfer (slave API support to come). I used dmatest client without problem in different configurations to test it. Full documentation for this controller can be found in the SAM9RL datasheet: http://www.atmel.com/dyn/products/product_card.asp?part_id=4243 Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-03 19:24:33 +02:00
dmaengine: Kconfig: fix Atmel at_hdmac entry Remove SoC dependency and make it generic for every Atmel ARM AT91. That will allow to select this driver for newer chips. Keep dependency on AT91 because of the use of an header file located in include/mach directory. Modify the comment to reflect this. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
2012-03-15 11:31:58 +01:00
I/OAT: Add DCA services Add code to connect to the DCA driver and provide cpu tags for use by drivers that would like to use Direct Cache Access hints. [Adrian Bunk] Several Kconfig cleanup items [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when built for uni-processor Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 01:27:42 -07:00
dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver New atmel DMA controller known as XDMAC, introduced with SAMA5D4 devices. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-10-22 17:22:18 +02:00
dmaengine: at_xdmac: prefer usage of readl/writel_relaxed _relaxed version of readl and writel are not implemented on all architecture so COMPILE_TEST has to be removed in order to not cause some build failures. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-11-13 11:52:39 +01:00
dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver New atmel DMA controller known as XDMAC, introduced with SAMA5D4 devices. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-10-22 17:22:18 +02:00
I/OAT: Add DCA services Add code to connect to the DCA driver and provide cpu tags for use by drivers that would like to use Direct Cache Access hints. [Adrian Bunk] Several Kconfig cleanup items [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when built for uni-processor Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 01:27:42 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: axi-dmac: extend support for ZynqMP arch The AXI DMAC driver is currently supported also on the Xilinx ZynqMP architecture. This change allows this driver to be enabled & used on it as well. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-02-28 14:39:43 +02:00
I/OAT: Add DCA services Add code to connect to the DCA driver and provide cpu tags for use by drivers that would like to use Direct Cache Access hints. [Adrian Bunk] Several Kconfig cleanup items [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when built for uni-processor Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 01:27:42 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: axi-dmac: add regmap support The registers for AXI DMAC are detailed at: https://wiki.analog.com/resources/fpga/docs/axi_dmac#register_map This change adds regmap support for these registers, in case some wants to have a more direct access to them via this interface. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> [vkoul: fixed code style issue] Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-06-06 13:45:50 +03:00
I/OAT: Add DCA services Add code to connect to the DCA driver and provide cpu tags for use by drivers that would like to use Direct Cache Access hints. [Adrian Bunk] Several Kconfig cleanup items [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when built for uni-processor Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 01:27:42 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
[I/OAT]: DMA memcpy subsystem Provides an API for offloading memory copies to DMA devices Signed-off-by: Chris Leech <christopher.leech@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-05-23 17:18:44 -07:00
dmaengine: Add Broadcom SBA RAID driver The Broadcom stream buffer accelerator (SBA) provides offloading capabilities for RAID operations. This SBA offload engine is accessible via Broadcom SoC specific ring manager. This patch adds Broadcom SBA RAID driver which provides one DMA device with RAID capabilities using one or more Broadcom SoC specific ring manager channels. The SBA RAID driver in its current shape implements memcpy, xor, and pq operations. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-05-15 10:34:54 +05:30
dmaengine: bcm-sba-raid: fix Kconfig dependencies The new driver requires both mailbox and raid support for compile testing: drivers/dma/built-in.o: In function `sba_remove': edma.c:(.text+0x4414): undefined reference to `mbox_free_channel' drivers/dma/built-in.o: In function `sba_issue_pending': edma.c:(.text+0x46cc): undefined reference to `mbox_send_message' drivers/dma/built-in.o: In function `sba_probe': edma.c:(.text+0x4e60): undefined reference to `mbox_request_channel' edma.c:(.text+0x5038): undefined reference to `mbox_free_channel' drivers/dma/built-in.o: In function `sba_tx_status': edma.c:(.text+0x5210): undefined reference to `mbox_client_peek_data' drivers/dma/built-in.o: In function `sba_prep_dma_pq_req': edma.c:(.text+0x5784): undefined reference to `raid6_gflog' edma.c:(.text+0x5798): undefined reference to `raid6_gflog' This rearranges the Kconfig dependencies accordingly. Fixes: 743e1c8ffe4e ("dmaengine: Add Broadcom SBA RAID driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-05-18 15:25:25 +02:00
dmaengine: Add Broadcom SBA RAID driver The Broadcom stream buffer accelerator (SBA) provides offloading capabilities for RAID operations. This SBA offload engine is accessible via Broadcom SoC specific ring manager. This patch adds Broadcom SBA RAID driver which provides one DMA device with RAID capabilities using one or more Broadcom SoC specific ring manager channels. The SBA RAID driver in its current shape implements memcpy, xor, and pq operations. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-05-15 10:34:54 +05:30
dmaengine: Build bcm-sba-raid driver as loadable module for iProc SoCs By default, we build Broadcom SBA RAID driver as loadable module for iProc SOCs so that kernel image is little smaller and we load SBA RAID driver only when required. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-10-03 10:53:00 +05:30
dmaengine: Add Broadcom SBA RAID driver The Broadcom stream buffer accelerator (SBA) provides offloading capabilities for RAID operations. This SBA offload engine is accessible via Broadcom SoC specific ring manager. This patch adds Broadcom SBA RAID driver which provides one DMA device with RAID capabilities using one or more Broadcom SoC specific ring manager channels. The SBA RAID driver in its current shape implements memcpy, xor, and pq operations. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-05-15 10:34:54 +05:30
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: coh901318: enable COMPILE_TEST To get more coverage, enable COMPILE_TEST for this driver. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-09-02 15:29:49 +05:30
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: dma-jz4780: Don't depend on MACH_JZ4780 If we make this driver depend on MACH_JZ4780, that means it can be enabled only if we're building a kernel specially crafted for a JZ4780-based board, while most GNU/Linux distributions will want one generic MIPS kernel that works on multiple boards. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-08-29 23:32:48 +02:00
dmaengine: add a driver for Intel integrated DMA 64-bit Intel integrated DMA (iDMA) 64-bit is a specific IP that is used as a part of LPSS devices such as HSUART or SPI. The iDMA IP is attached for private usage on each host controller independently. While it has similarities with Synopsys DesignWare DMA, the following distinctions doesn't allow to use the existing driver: - 64-bit mode with corresponding changes in Hardware Linked List data structure - many slight differences in the channel registers Moreover this driver is based on the DMA virtual channels framework that helps to make the driver cleaner and easy to understand. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-07-27 18:04:02 +03:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: add a driver for Intel integrated DMA 64-bit Intel integrated DMA (iDMA) 64-bit is a specific IP that is used as a part of LPSS devices such as HSUART or SPI. The iDMA IP is attached for private usage on each host controller independently. While it has similarities with Synopsys DesignWare DMA, the following distinctions doesn't allow to use the existing driver: - 64-bit mode with corresponding changes in Hardware Linked List data structure - many slight differences in the channel registers Moreover this driver is based on the DMA virtual channels framework that helps to make the driver cleaner and easy to understand. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-07-27 18:04:02 +03:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: sa11x0: enable COMPILE_TEST To get more coverage, enable COMPILE_TEST for this driver. Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-09-02 15:31:42 +05:30
dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller This AHB DMA Controller (aka HDMA or DMAC on AT91 systems) is availlable on at91sam9rl chip. It will be used on other products in the future. This first release covers only the memory-to-memory tranfer type. This is the only tranfer type supported by this chip. On other products, it will be used also for peripheral DMA transfer (slave API support to come). I used dmatest client without problem in different configurations to test it. Full documentation for this controller can be found in the SAM9RL datasheet: http://www.atmel.com/dyn/products/product_card.asp?part_id=4243 Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-03 19:24:33 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller This AHB DMA Controller (aka HDMA or DMAC on AT91 systems) is availlable on at91sam9rl chip. It will be used on other products in the future. This first release covers only the memory-to-memory tranfer type. This is the only tranfer type supported by this chip. On other products, it will be used also for peripheral DMA transfer (slave API support to come). I used dmatest client without problem in different configurations to test it. Full documentation for this controller can be found in the SAM9RL datasheet: http://www.atmel.com/dyn/products/product_card.asp?part_id=4243 Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-03 19:24:33 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller This AHB DMA Controller (aka HDMA or DMAC on AT91 systems) is availlable on at91sam9rl chip. It will be used on other products in the future. This first release covers only the memory-to-memory tranfer type. This is the only tranfer type supported by this chip. On other products, it will be used also for peripheral DMA transfer (slave API support to come). I used dmatest client without problem in different configurations to test it. Full documentation for this controller can be found in the SAM9RL datasheet: http://www.atmel.com/dyn/products/product_card.asp?part_id=4243 Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-03 19:24:33 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine updates for 4.3-rc1 This time we have aded a new capability for scatter-gathered memset using dmaengine APIs. This is supported in xdmac & hdmac drivers We have added support for reusing descriptors for examples like video buffers etc. Driver will follow The behaviour of descriptor ack has been clarified and documented New devices added are: - dma controller in sun[457]i SoCs - lpc18xx dmamux - ZTE ZX296702 dma controller - Analog Devices AXI-DMAC DMA controller - eDMA support for dma-crossbar - imx6sx support in imx-sdma driver - imx-sdma device to device support Others - jz4780 fixes - ioatdma large refactor and cleanup for removal of ioat v1 and v2 which is deprecated and fixes - ACPI support in X-Gene DMA engine driver - ipu irq fixes - mvxor fixes - minor fixes spread thru drivers -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV5+nSAAoJEHwUBw8lI4NHiXQQAI/++7PmUGZ6BDZGu0B9Bj7U JalNijm43p858nka1zVhDea8pi7Cq3zJdE8EAB7FPQGESvCODWr62oZBr+mSaQ1C oU1RTIRTSiU2HPE4EFeGUvVGrnmTbHR2b1apI1SU41gKn+oQ5RJRRoQwEVwO6uuZ 1VYcUqhurIAZs1FrMIAUa2vg7KTcK9UotfwR2gGBmSvXMf1aJ/dNZC7i/pBJjoyt v6KrLuYjEBAJvY7l368+NhLY/MS+2xdCMQo84B+HNEG7eA7y2MFOcRPXQA3a7dzr NwNuAZcTYDU11r2jiAPcnBM5sPo4bokX6Td0oDbYH6Rn2uIWlof7jGIceUaWLQQq QGZc4QPI4KdjTGNedRN8g9zqv0irFVfDr5v1A+B7N7ehvlubnB4jV8LmLpqN6UQH B38VnDJ3hqdZ6j9RHQTyUoQskSYMPbOAUYbL0qQLkyx8AnLc8TRv7DgtSvZjnz5W oF6So2A5SWZ7UmXKupd6TKtdyG3xtFAh+/MGVQ1RS9bCmnyhaIxJRiJwfftCBTBx IZePOsqlwl2dojM62BDlGS4CLRZve2VgiUEJaPINsdm/On3tQs9+iDbNY3cpvLQS P9u4po1TQPZnKG732vPAxEqdlq709kta7Fj5KIEvNjuWBBGKfypNP8BHKRvTLFlR kcbO03NzwSO6PZpmiUsx =gQZ6 -----END PGP SIGNATURE----- Merge tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma Pull dmaengine updates from Vinod Koul: "This time we have aded a new capability for scatter-gathered memset using dmaengine APIs. This is supported in xdmac & hdmac drivers We have added support for reusing descriptors for examples like video buffers etc. Driver will follow The behaviour of descriptor ack has been clarified and documented New devices added are: - dma controller in sun[457]i SoCs - lpc18xx dmamux - ZTE ZX296702 dma controller - Analog Devices AXI-DMAC DMA controller - eDMA support for dma-crossbar - imx6sx support in imx-sdma driver - imx-sdma device to device support Other: - jz4780 fixes - ioatdma large refactor and cleanup for removal of ioat v1 and v2 which is deprecated and fixes - ACPI support in X-Gene DMA engine driver - ipu irq fixes - mvxor fixes - minor fixes spread thru drivers" [ The Kconfig and Makefile entries got re-sorted alphabetically, and I handled the conflict with the new Intel integrated IDMA driver by slightly mis-sorting it on purpose: "IDMA64" got sorted after "IMX" in order to keep the Intel entries together. I think it might be a good idea to just rename the IDMA64 config entry to INTEL_IDMA64 to make the sorting be a true sort, not this mismash. Also, this merge disables the COMPILE_TEST for the sun4i DMA controller, because it does not compile cleanly at all. - Linus ] * tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (89 commits) dmaengine: ioatdma: add Broadwell EP ioatdma PCI dev IDs dmaengine :ipu: change ipu_irq_handler() to remove compile warning dmaengine: ioatdma: Fix variable array length dmaengine: ioatdma: fix sparse "error" with prep lock dmaengine: hdmac: Add memset capabilities dmaengine: sort the sh Makefile dmaengine: sort the sh Kconfig dmaengine: sort the dw Kconfig dmaengine: sort the Kconfig dmaengine: sort the makefile drivers/dma: make mv_xor.c driver explicitly non-modular dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller devicetree: Add bindings documentation for Analog Devices AXI-DMAC dmaengine: xgene-dma: Fix the lock to allow client for further submission of requests dmaengine: ioatdma: fix coccinelle warning dmaengine: ioatdma: fix zero day warning on incompatible pointer type dmaengine: tegra-apb: Simplify locking for device using global pause dmaengine: tegra-apb: Remove unnecessary return statements and variables dmaengine: tegra-apb: Avoid unnecessary channel base address calculation dmaengine: tegra-apb: Remove unused variables ...
2015-09-04 11:10:18 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver New atmel DMA controller known as XDMAC, introduced with SAMA5D4 devices. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-10-22 17:22:18 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver New atmel DMA controller known as XDMAC, introduced with SAMA5D4 devices. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-10-22 17:22:18 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: sun6i: allow build on ARM64 platforms (sun50i) As 64-bit Allwinner H5 SoC has the same DMA engine with H3, the DMA driver should be allowed to be built for ARM64, in order to make it work on H5. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-01-29 10:33:29 +08:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: Introduce DW AXI DMAC driver This patch adds support for the DW AXI DMAC controller. DW AXI DMAC is a part of HSDK development board from Synopsys. In this driver implementation only DMA_MEMCPY transfers are supported. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2018-03-06 14:46:14 +03:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: ep93xx: enable COMPILE_TEST To get more coverage, enable COMPILE_TEST for this driver. Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-09-02 15:38:43 +05:30
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver New atmel DMA controller known as XDMAC, introduced with SAMA5D4 devices. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-10-22 17:22:18 +02:00
dmaengine: add driver for Freescale MPC85xx DMA controller The driver implements DMA engine API for Freescale MPC85xx DMA controller, which could be used by devices in the silicon. The driver supports the Basic mode of Freescale MPC85xx DMA controller. The MPC85xx processors supported include MPC8540/60, MPC8555, MPC8548, MPC8641 and so on. The MPC83xx(MPC8349, MPC8360) are also supported. [kamalesh@linux.vnet.ibm.com: build fix] [dan.j.williams@intel.com: merge mm fixes, rebase on async_tx-2.6.25] Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com> Acked-by: Kumar Gala <galak@gate.crashing.org> Cc: Shannon Nelson <shannon.nelson@intel.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-03-01 07:42:48 -07:00
DMA: Freescale: update driver to support 8-channel DMA engine This patch adds support to 8-channel DMA engine, thus the driver works for both the new 8-channel and the legacy 4-channel DMA engines. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-09-26 17:33:43 +08:00
fsldma: allow Freescale Elo DMA driver to be compiled as a module Modify the Freescale Elo / Elo Plus DMA driver so that it can be compiled as a module. The primary change is to stop treating the DMA controller as a bus, and the DMA channels as devices on the bus. This is because the Open Firmware (OF) kernel code does not allow busses to be removed, so although we can call of_platform_bus_probe() to probe the DMA channels, there is no of_platform_bus_remove(). Instead, the DMA channels are manually probed, similar to what fsl_elbc_nand.c does. Cc: Scott Wood <scottwood@freescale.com> Acked-by: Li Yang <leoli@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-09-26 17:00:11 -07:00
dmaengine: add driver for Freescale MPC85xx DMA controller The driver implements DMA engine API for Freescale MPC85xx DMA controller, which could be used by devices in the silicon. The driver supports the Basic mode of Freescale MPC85xx DMA controller. The MPC85xx processors supported include MPC8540/60, MPC8555, MPC8548, MPC8641 and so on. The MPC83xx(MPC8349, MPC8360) are also supported. [kamalesh@linux.vnet.ibm.com: build fix] [dan.j.williams@intel.com: merge mm fixes, rebase on async_tx-2.6.25] Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com> Acked-by: Kumar Gala <galak@gate.crashing.org> Cc: Shannon Nelson <shannon.nelson@intel.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-03-01 07:42:48 -07:00
async_tx: make async_tx channel switching opt-in The majority of drivers in drivers/dma/ will never establish cross channel operation chains and do not need the extra overhead in struct dma_async_tx_descriptor. Make channel switching opt-in by default. Cc: Anatolij Gustschin <agust@denx.de> Cc: Ira Snyder <iws@ovro.caltech.edu> Cc: Linus Walleij <linus.walleij@stericsson.com> Cc: Saeed Bishara <saeed@marvell.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-10-07 16:44:50 -07:00
dmaengine: add driver for Freescale MPC85xx DMA controller The driver implements DMA engine API for Freescale MPC85xx DMA controller, which could be used by devices in the silicon. The driver supports the Basic mode of Freescale MPC85xx DMA controller. The MPC85xx processors supported include MPC8540/60, MPC8555, MPC8548, MPC8641 and so on. The MPC83xx(MPC8349, MPC8360) are also supported. [kamalesh@linux.vnet.ibm.com: build fix] [dan.j.williams@intel.com: merge mm fixes, rebase on async_tx-2.6.25] Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com> Acked-by: Kumar Gala <galak@gate.crashing.org> Cc: Shannon Nelson <shannon.nelson@intel.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-03-01 07:42:48 -07:00
DMA: Freescale: update driver to support 8-channel DMA engine This patch adds support to 8-channel DMA engine, thus the driver works for both the new 8-channel and the legacy 4-channel DMA engines. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-09-26 17:33:43 +08:00
dmaengine: add driver for Freescale MPC85xx DMA controller The driver implements DMA engine API for Freescale MPC85xx DMA controller, which could be used by devices in the silicon. The driver supports the Basic mode of Freescale MPC85xx DMA controller. The MPC85xx processors supported include MPC8540/60, MPC8555, MPC8548, MPC8641 and so on. The MPC83xx(MPC8349, MPC8360) are also supported. [kamalesh@linux.vnet.ibm.com: build fix] [dan.j.williams@intel.com: merge mm fixes, rebase on async_tx-2.6.25] Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com> Acked-by: Kumar Gala <galak@gate.crashing.org> Cc: Shannon Nelson <shannon.nelson@intel.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-03-01 07:42:48 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs NXP Queue DMA controller(qDMA) on Layerscape SoCs supports channel virtuallization by allowing DMA jobs to be enqueued into different command queues. Signed-off-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Jiaheng Fan <jiaheng.fan@nxp.com> Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-10-30 10:36:00 +08:00
dmaengine: Fix Kconfig indentation Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^ /\t/' -i */Kconfig Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/1574306348-29212-1-git-send-email-krzk@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-11-21 04:19:08 +01:00
dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs NXP Queue DMA controller(qDMA) on Layerscape SoCs supports channel virtuallization by allowing DMA jobs to be enqueued into different command queues. Signed-off-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Jiaheng Fan <jiaheng.fan@nxp.com> Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-10-30 10:36:00 +08:00
dmaengine: Driver support for FSL RaidEngine device. The RaidEngine is a new FSL hardware used for Raid5/6 acceration. This patch enables the RaidEngine functionality and provides hardware offloading capability for memcpy, xor and pq computation. It works with async_tx. Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Signed-off-by: Xuelin Shi <xuelin.shi@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-03-03 14:26:22 +08:00
dmaengine: Fix Kconfig indentation Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^ /\t/' -i */Kconfig Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/1574306348-29212-1-git-send-email-krzk@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-11-21 04:19:08 +01:00
dmaengine: Driver support for FSL RaidEngine device. The RaidEngine is a new FSL hardware used for Raid5/6 acceration. This patch enables the RaidEngine functionality and provides hardware offloading capability for memcpy, xor and pq computation. It works with async_tx. Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Signed-off-by: Xuelin Shi <xuelin.shi@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-03-03 14:26:22 +08:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dma: Add MPC512x DMA driver Adds initial version of MPC512x DMA driver. Only memory to memory transfers are currenly supported. Signed-off-by: Piotr Ziecik <kosmo@semihalf.com> Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: John Rigby <jcrigby@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-02-05 03:42:52 +00:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
powerpc, dma: move bestcomm driver from arch/powerpc/sysdev to drivers/dma The bestcomm dma hardware, and some of its users like the FEC ethernet component, is used in different FreeScale parts, including non-powerpc parts like the ColdFire MCF547x & MCF548x families. Don't keep the driver hidden in arch/powerpc where it is inaccessible for other arches. .c files are moved to drivers/dma/bestcomm, while .h files are moved to include/linux/fsl/bestcomm. Makefiles, Kconfigs and #include directives are updated for the new file locations. Tested by recompiling for MPC5200 with all bestcomm users enabled. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Anatolij Gustschin <agust@denx.de>
2012-10-12 17:52:45 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dma i.MX: remove individual SOC dependency The individual SoC dependency in Kconfig hardly scales anymore. Instead of having such a fine grained dependency just depend on ARCH_MXC and risk that the uninformed user has to look in the help text to figure out which driver is the correct one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2011-08-24 08:41:09 +02:00
dmaengine: DMA engine driver for Marvell XOR engine The XOR engine found in Marvell's SoCs and system controllers provides XOR and DMA operation, iSCSI CRC32C calculation, memory initialization, and memory ECC error cleanup operation support. This driver implements the DMA engine API and supports the following capabilities: - memcpy - xor - memset The XOR engine can be used by DMA engine clients implemented in the kernel, one of those clients is the RAID module. In that case, I observed 20% improvement in the raid5 write throughput, and 40% decrease in the CPU utilization when doing array construction, those results obtained on an 5182 running at 500Mhz. When enabling the NET DMA client, the performance decreased, so meanwhile it is recommended to keep this client off. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-08 11:58:36 -07:00
i.MX31: Image Processing Unit DMA and IRQ drivers i.MX3x SoCs contain an Image Processing Unit, consisting of a Control Module (CM), Display Interface (DI), Synchronous Display Controller (SDC), Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter (PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC). CM contains, among other blocks, an Interrupt Generator (IG) and a Clock and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are supported over dmaengine and irq-chip APIs respectively. IDMAC is a specialised DMA controller, its DMA channels cannot be used for general-purpose operations, even though it might be possible to configure a memory-to-memory channel for memcpy operation. This driver will not work with generic dmaengine clients, clients, wishing to use it must use respective wrapper structures, they also must specify which channels they require, as channels are hard-wired to specific IPU functions. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-19 15:36:21 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: DMA engine driver for Marvell XOR engine The XOR engine found in Marvell's SoCs and system controllers provides XOR and DMA operation, iSCSI CRC32C calculation, memory initialization, and memory ECC error cleanup operation support. This driver implements the DMA engine API and supports the following capabilities: - memcpy - xor - memset The XOR engine can be used by DMA engine clients implemented in the kernel, one of those clients is the RAID module. In that case, I observed 20% improvement in the raid5 write throughput, and 40% decrease in the CPU utilization when doing array construction, those results obtained on an 5182 running at 500Mhz. When enabling the NET DMA client, the performance decreased, so meanwhile it is recommended to keep this client off. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-08 11:58:36 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dma i.MX: remove individual SOC dependency The individual SoC dependency in Kconfig hardly scales anymore. Instead of having such a fine grained dependency just depend on ARCH_MXC and risk that the uninformed user has to look in the help text to figure out which driver is the correct one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2011-08-24 08:41:09 +02:00
i.MX31: Image Processing Unit DMA and IRQ drivers i.MX3x SoCs contain an Image Processing Unit, consisting of a Control Module (CM), Display Interface (DI), Synchronous Display Controller (SDC), Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter (PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC). CM contains, among other blocks, an Interrupt Generator (IG) and a Clock and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are supported over dmaengine and irq-chip APIs respectively. IDMAC is a specialised DMA controller, its DMA channels cannot be used for general-purpose operations, even though it might be possible to configure a memory-to-memory channel for memcpy operation. This driver will not work with generic dmaengine clients, clients, wishing to use it must use respective wrapper structures, they also must specify which channels they require, as channels are hard-wired to specific IPU functions. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-19 15:36:21 -07:00
dmaengine: imx-sdma: add virt-dma support The legacy sdma driver has below limitations or drawbacks: 1. Hardcode the max BDs number as "PAGE_SIZE / sizeof(*)", and alloc one page size for one channel regardless of only few BDs needed most time. But in few cases, the max PAGE_SIZE maybe not enough. 2. One SDMA channel can't stop immediatley once channel disabled which means SDMA interrupt may come in after this channel terminated.There are some patches for this corner case such as commit "2746e2c389f9", but not cover non-cyclic. The common virt-dma overcomes the above limitations. It can alloc bd dynamically and free bd once this tx transfer done. No memory wasted or maximum limititation here, only depends on how many memory can be requested from kernel. For No.2, such issue can be workaround by checking if there is available descript("sdmac->desc") now once the unwanted interrupt coming. At last the common virt-dma is easier for sdma driver maintain. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-06-20 00:57:00 +08:00
i.MX31: Image Processing Unit DMA and IRQ drivers i.MX3x SoCs contain an Image Processing Unit, consisting of a Control Module (CM), Display Interface (DI), Synchronous Display Controller (SDC), Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter (PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC). CM contains, among other blocks, an Interrupt Generator (IG) and a Clock and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are supported over dmaengine and irq-chip APIs respectively. IDMAC is a specialised DMA controller, its DMA channels cannot be used for general-purpose operations, even though it might be possible to configure a memory-to-memory channel for memcpy operation. This driver will not work with generic dmaengine clients, clients, wishing to use it must use respective wrapper structures, they also must specify which channels they require, as channels are hard-wired to specific IPU functions. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-19 15:36:21 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
i.MX31: Image Processing Unit DMA and IRQ drivers i.MX3x SoCs contain an Image Processing Unit, consisting of a Control Module (CM), Display Interface (DI), Synchronous Display Controller (SDC), Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter (PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC). CM contains, among other blocks, an Interrupt Generator (IG) and a Clock and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are supported over dmaengine and irq-chip APIs respectively. IDMAC is a specialised DMA controller, its DMA channels cannot be used for general-purpose operations, even though it might be possible to configure a memory-to-memory channel for memcpy operation. This driver will not work with generic dmaengine clients, clients, wishing to use it must use respective wrapper structures, they also must specify which channels they require, as channels are hard-wired to specific IPU functions. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-19 15:36:21 -07:00
dmaengine: idma: rename to INTEL_IDMA64 the symbol CONFIG_IDMA64 should rather be CONFIG_INTEL_IDMA64 to conform to rest of the intel dmaengine drivers. This was found after sorting the entries and trying to place this odd one Suggested-by: Linus Torvalds <torvalds@linux-foundation.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-09-21 22:18:45 +05:30
dmaengine updates for 4.3-rc1 This time we have aded a new capability for scatter-gathered memset using dmaengine APIs. This is supported in xdmac & hdmac drivers We have added support for reusing descriptors for examples like video buffers etc. Driver will follow The behaviour of descriptor ack has been clarified and documented New devices added are: - dma controller in sun[457]i SoCs - lpc18xx dmamux - ZTE ZX296702 dma controller - Analog Devices AXI-DMAC DMA controller - eDMA support for dma-crossbar - imx6sx support in imx-sdma driver - imx-sdma device to device support Others - jz4780 fixes - ioatdma large refactor and cleanup for removal of ioat v1 and v2 which is deprecated and fixes - ACPI support in X-Gene DMA engine driver - ipu irq fixes - mvxor fixes - minor fixes spread thru drivers -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV5+nSAAoJEHwUBw8lI4NHiXQQAI/++7PmUGZ6BDZGu0B9Bj7U JalNijm43p858nka1zVhDea8pi7Cq3zJdE8EAB7FPQGESvCODWr62oZBr+mSaQ1C oU1RTIRTSiU2HPE4EFeGUvVGrnmTbHR2b1apI1SU41gKn+oQ5RJRRoQwEVwO6uuZ 1VYcUqhurIAZs1FrMIAUa2vg7KTcK9UotfwR2gGBmSvXMf1aJ/dNZC7i/pBJjoyt v6KrLuYjEBAJvY7l368+NhLY/MS+2xdCMQo84B+HNEG7eA7y2MFOcRPXQA3a7dzr NwNuAZcTYDU11r2jiAPcnBM5sPo4bokX6Td0oDbYH6Rn2uIWlof7jGIceUaWLQQq QGZc4QPI4KdjTGNedRN8g9zqv0irFVfDr5v1A+B7N7ehvlubnB4jV8LmLpqN6UQH B38VnDJ3hqdZ6j9RHQTyUoQskSYMPbOAUYbL0qQLkyx8AnLc8TRv7DgtSvZjnz5W oF6So2A5SWZ7UmXKupd6TKtdyG3xtFAh+/MGVQ1RS9bCmnyhaIxJRiJwfftCBTBx IZePOsqlwl2dojM62BDlGS4CLRZve2VgiUEJaPINsdm/On3tQs9+iDbNY3cpvLQS P9u4po1TQPZnKG732vPAxEqdlq709kta7Fj5KIEvNjuWBBGKfypNP8BHKRvTLFlR kcbO03NzwSO6PZpmiUsx =gQZ6 -----END PGP SIGNATURE----- Merge tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma Pull dmaengine updates from Vinod Koul: "This time we have aded a new capability for scatter-gathered memset using dmaengine APIs. This is supported in xdmac & hdmac drivers We have added support for reusing descriptors for examples like video buffers etc. Driver will follow The behaviour of descriptor ack has been clarified and documented New devices added are: - dma controller in sun[457]i SoCs - lpc18xx dmamux - ZTE ZX296702 dma controller - Analog Devices AXI-DMAC DMA controller - eDMA support for dma-crossbar - imx6sx support in imx-sdma driver - imx-sdma device to device support Other: - jz4780 fixes - ioatdma large refactor and cleanup for removal of ioat v1 and v2 which is deprecated and fixes - ACPI support in X-Gene DMA engine driver - ipu irq fixes - mvxor fixes - minor fixes spread thru drivers" [ The Kconfig and Makefile entries got re-sorted alphabetically, and I handled the conflict with the new Intel integrated IDMA driver by slightly mis-sorting it on purpose: "IDMA64" got sorted after "IMX" in order to keep the Intel entries together. I think it might be a good idea to just rename the IDMA64 config entry to INTEL_IDMA64 to make the sorting be a true sort, not this mismash. Also, this merge disables the COMPILE_TEST for the sun4i DMA controller, because it does not compile cleanly at all. - Linus ] * tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (89 commits) dmaengine: ioatdma: add Broadwell EP ioatdma PCI dev IDs dmaengine :ipu: change ipu_irq_handler() to remove compile warning dmaengine: ioatdma: Fix variable array length dmaengine: ioatdma: fix sparse "error" with prep lock dmaengine: hdmac: Add memset capabilities dmaengine: sort the sh Makefile dmaengine: sort the sh Kconfig dmaengine: sort the dw Kconfig dmaengine: sort the Kconfig dmaengine: sort the makefile drivers/dma: make mv_xor.c driver explicitly non-modular dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller devicetree: Add bindings documentation for Analog Devices AXI-DMAC dmaengine: xgene-dma: Fix the lock to allow client for further submission of requests dmaengine: ioatdma: fix coccinelle warning dmaengine: ioatdma: fix zero day warning on incompatible pointer type dmaengine: tegra-apb: Simplify locking for device using global pause dmaengine: tegra-apb: Remove unnecessary return statements and variables dmaengine: tegra-apb: Avoid unnecessary channel base address calculation dmaengine: tegra-apb: Remove unused variables ...
2015-09-04 11:10:18 -07:00
i.MX31: Image Processing Unit DMA and IRQ drivers i.MX3x SoCs contain an Image Processing Unit, consisting of a Control Module (CM), Display Interface (DI), Synchronous Display Controller (SDC), Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter (PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC). CM contains, among other blocks, an Interrupt Generator (IG) and a Clock and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are supported over dmaengine and irq-chip APIs respectively. IDMAC is a specialised DMA controller, its DMA channels cannot be used for general-purpose operations, even though it might be possible to configure a memory-to-memory channel for memcpy operation. This driver will not work with generic dmaengine clients, clients, wishing to use it must use respective wrapper structures, they also must specify which channels they require, as channels are hard-wired to specific IPU functions. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-19 15:36:21 -07:00
dmaengine updates for 4.3-rc1 This time we have aded a new capability for scatter-gathered memset using dmaengine APIs. This is supported in xdmac & hdmac drivers We have added support for reusing descriptors for examples like video buffers etc. Driver will follow The behaviour of descriptor ack has been clarified and documented New devices added are: - dma controller in sun[457]i SoCs - lpc18xx dmamux - ZTE ZX296702 dma controller - Analog Devices AXI-DMAC DMA controller - eDMA support for dma-crossbar - imx6sx support in imx-sdma driver - imx-sdma device to device support Others - jz4780 fixes - ioatdma large refactor and cleanup for removal of ioat v1 and v2 which is deprecated and fixes - ACPI support in X-Gene DMA engine driver - ipu irq fixes - mvxor fixes - minor fixes spread thru drivers -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV5+nSAAoJEHwUBw8lI4NHiXQQAI/++7PmUGZ6BDZGu0B9Bj7U JalNijm43p858nka1zVhDea8pi7Cq3zJdE8EAB7FPQGESvCODWr62oZBr+mSaQ1C oU1RTIRTSiU2HPE4EFeGUvVGrnmTbHR2b1apI1SU41gKn+oQ5RJRRoQwEVwO6uuZ 1VYcUqhurIAZs1FrMIAUa2vg7KTcK9UotfwR2gGBmSvXMf1aJ/dNZC7i/pBJjoyt v6KrLuYjEBAJvY7l368+NhLY/MS+2xdCMQo84B+HNEG7eA7y2MFOcRPXQA3a7dzr NwNuAZcTYDU11r2jiAPcnBM5sPo4bokX6Td0oDbYH6Rn2uIWlof7jGIceUaWLQQq QGZc4QPI4KdjTGNedRN8g9zqv0irFVfDr5v1A+B7N7ehvlubnB4jV8LmLpqN6UQH B38VnDJ3hqdZ6j9RHQTyUoQskSYMPbOAUYbL0qQLkyx8AnLc8TRv7DgtSvZjnz5W oF6So2A5SWZ7UmXKupd6TKtdyG3xtFAh+/MGVQ1RS9bCmnyhaIxJRiJwfftCBTBx IZePOsqlwl2dojM62BDlGS4CLRZve2VgiUEJaPINsdm/On3tQs9+iDbNY3cpvLQS P9u4po1TQPZnKG732vPAxEqdlq709kta7Fj5KIEvNjuWBBGKfypNP8BHKRvTLFlR kcbO03NzwSO6PZpmiUsx =gQZ6 -----END PGP SIGNATURE----- Merge tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma Pull dmaengine updates from Vinod Koul: "This time we have aded a new capability for scatter-gathered memset using dmaengine APIs. This is supported in xdmac & hdmac drivers We have added support for reusing descriptors for examples like video buffers etc. Driver will follow The behaviour of descriptor ack has been clarified and documented New devices added are: - dma controller in sun[457]i SoCs - lpc18xx dmamux - ZTE ZX296702 dma controller - Analog Devices AXI-DMAC DMA controller - eDMA support for dma-crossbar - imx6sx support in imx-sdma driver - imx-sdma device to device support Other: - jz4780 fixes - ioatdma large refactor and cleanup for removal of ioat v1 and v2 which is deprecated and fixes - ACPI support in X-Gene DMA engine driver - ipu irq fixes - mvxor fixes - minor fixes spread thru drivers" [ The Kconfig and Makefile entries got re-sorted alphabetically, and I handled the conflict with the new Intel integrated IDMA driver by slightly mis-sorting it on purpose: "IDMA64" got sorted after "IMX" in order to keep the Intel entries together. I think it might be a good idea to just rename the IDMA64 config entry to INTEL_IDMA64 to make the sorting be a true sort, not this mismash. Also, this merge disables the COMPILE_TEST for the sun4i DMA controller, because it does not compile cleanly at all. - Linus ] * tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (89 commits) dmaengine: ioatdma: add Broadwell EP ioatdma PCI dev IDs dmaengine :ipu: change ipu_irq_handler() to remove compile warning dmaengine: ioatdma: Fix variable array length dmaengine: ioatdma: fix sparse "error" with prep lock dmaengine: hdmac: Add memset capabilities dmaengine: sort the sh Makefile dmaengine: sort the sh Kconfig dmaengine: sort the dw Kconfig dmaengine: sort the Kconfig dmaengine: sort the makefile drivers/dma: make mv_xor.c driver explicitly non-modular dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller devicetree: Add bindings documentation for Analog Devices AXI-DMAC dmaengine: xgene-dma: Fix the lock to allow client for further submission of requests dmaengine: ioatdma: fix coccinelle warning dmaengine: ioatdma: fix zero day warning on incompatible pointer type dmaengine: tegra-apb: Simplify locking for device using global pause dmaengine: tegra-apb: Remove unnecessary return statements and variables dmaengine: tegra-apb: Avoid unnecessary channel base address calculation dmaengine: tegra-apb: Remove unused variables ...
2015-09-04 11:10:18 -07:00
i.MX31: Image Processing Unit DMA and IRQ drivers i.MX3x SoCs contain an Image Processing Unit, consisting of a Control Module (CM), Display Interface (DI), Synchronous Display Controller (SDC), Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter (PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC). CM contains, among other blocks, an Interrupt Generator (IG) and a Clock and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are supported over dmaengine and irq-chip APIs respectively. IDMAC is a specialised DMA controller, its DMA channels cannot be used for general-purpose operations, even though it might be possible to configure a memory-to-memory channel for memcpy operation. This driver will not work with generic dmaengine clients, clients, wishing to use it must use respective wrapper structures, they also must specify which channels they require, as channels are hard-wired to specific IPU functions. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-19 15:36:21 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: pxa: add pxa dmaengine driver This is a new driver for pxa SoCs, which is also compatible with the former mmp_pdma. The rationale behind a new driver (as opposed to incremental patching) was : - the new driver relies on virt-dma, which obsoletes all the internal structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the functions - mmp_pdma allocates dma coherent descriptors containing not only hardware descriptors but linked list information The new driver only puts the dma hardware descriptors (ie. 4 u32) into the dma pool allocated memory. This changes completely the way descriptors are handled - the architecture behind the interrupt/tasklet management was rewritten to be more conforming to virt-dma - the buffers alignment is handled differently The former driver assumed that the DMA channel stopped between each descriptor. The new one chains descriptors to let the channel running. This is a necessary guarantee for real-time high bandwidth usecases such as video capture on "old" architectures such as pxa. - hot chaining / cold chaining / no chaining Whenever possible, submitting a descriptor "hot chains" it to a running channel. There is still no guarantee that the descriptor will be issued, as the channel might be stopped just before the descriptor is submitted. Yet this allows to submit several video buffers, and resubmit a buffer while another is under handling. As before, dma_async_issue_pending() is the only guarantee to have all the buffers issued. When an alignment issue is detected (ie. one address in a descriptor is not a multiple of 8), if the already running channel is in "aligned mode", the channel will stop, and restarted in "misaligned mode" to finished the issued list. - descriptors reusing A submitted, issued and completed descriptor can be reused, ie resubmitted if it was prepared with the proper flag (DMA_PREP_ACK). Only a channel resources release will in this case release that buffer. This allows a rolling ring of buffers to be reused, where there are several thousands of hardware descriptors used (video buffer for example). Additionally, a set of more casual features is introduced : - debugging traces - lockless way to know if a descriptor is terminated or not The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x), with dmatest, pxa_camera and pxamci. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-25 23:29:20 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: pxa: add pxa dmaengine driver This is a new driver for pxa SoCs, which is also compatible with the former mmp_pdma. The rationale behind a new driver (as opposed to incremental patching) was : - the new driver relies on virt-dma, which obsoletes all the internal structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the functions - mmp_pdma allocates dma coherent descriptors containing not only hardware descriptors but linked list information The new driver only puts the dma hardware descriptors (ie. 4 u32) into the dma pool allocated memory. This changes completely the way descriptors are handled - the architecture behind the interrupt/tasklet management was rewritten to be more conforming to virt-dma - the buffers alignment is handled differently The former driver assumed that the DMA channel stopped between each descriptor. The new one chains descriptors to let the channel running. This is a necessary guarantee for real-time high bandwidth usecases such as video capture on "old" architectures such as pxa. - hot chaining / cold chaining / no chaining Whenever possible, submitting a descriptor "hot chains" it to a running channel. There is still no guarantee that the descriptor will be issued, as the channel might be stopped just before the descriptor is submitted. Yet this allows to submit several video buffers, and resubmit a buffer while another is under handling. As before, dma_async_issue_pending() is the only guarantee to have all the buffers issued. When an alignment issue is detected (ie. one address in a descriptor is not a multiple of 8), if the already running channel is in "aligned mode", the channel will stop, and restarted in "misaligned mode" to finished the issued list. - descriptors reusing A submitted, issued and completed descriptor can be reused, ie resubmitted if it was prepared with the proper flag (DMA_PREP_ACK). Only a channel resources release will in this case release that buffer. This allows a rolling ring of buffers to be reused, where there are several thousands of hardware descriptors used (video buffer for example). Additionally, a set of more casual features is introduced : - debugging traces - lockless way to know if a descriptor is terminated or not The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x), with dmatest, pxa_camera and pxamci. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-25 23:29:20 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: pxa: add pxa dmaengine driver This is a new driver for pxa SoCs, which is also compatible with the former mmp_pdma. The rationale behind a new driver (as opposed to incremental patching) was : - the new driver relies on virt-dma, which obsoletes all the internal structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the functions - mmp_pdma allocates dma coherent descriptors containing not only hardware descriptors but linked list information The new driver only puts the dma hardware descriptors (ie. 4 u32) into the dma pool allocated memory. This changes completely the way descriptors are handled - the architecture behind the interrupt/tasklet management was rewritten to be more conforming to virt-dma - the buffers alignment is handled differently The former driver assumed that the DMA channel stopped between each descriptor. The new one chains descriptors to let the channel running. This is a necessary guarantee for real-time high bandwidth usecases such as video capture on "old" architectures such as pxa. - hot chaining / cold chaining / no chaining Whenever possible, submitting a descriptor "hot chains" it to a running channel. There is still no guarantee that the descriptor will be issued, as the channel might be stopped just before the descriptor is submitted. Yet this allows to submit several video buffers, and resubmit a buffer while another is under handling. As before, dma_async_issue_pending() is the only guarantee to have all the buffers issued. When an alignment issue is detected (ie. one address in a descriptor is not a multiple of 8), if the already running channel is in "aligned mode", the channel will stop, and restarted in "misaligned mode" to finished the issued list. - descriptors reusing A submitted, issued and completed descriptor can be reused, ie resubmitted if it was prepared with the proper flag (DMA_PREP_ACK). Only a channel resources release will in this case release that buffer. This allows a rolling ring of buffers to be reused, where there are several thousands of hardware descriptors used (video buffer for example). Additionally, a set of more casual features is introduced : - debugging traces - lockless way to know if a descriptor is terminated or not The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x), with dmatest, pxa_camera and pxamci. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-25 23:29:20 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dma: iop-adma: allow building without platform headers Now that iop3xx and iop13xx are gone, the iop-adma driver no longer needs to deal with incompatible register layout defined in machine specific header files. Move the iop32x specific definitions into drivers/dma/iop-adma.h and the platform_data into include/linux/platform_data/dma-iop32x.h, and change the machine code to no longer reference those. The DMA0_ID/DMA1_ID/AAU_ID macros are required as part of the platform data interface and still need to be visible, so move those from one header to the other. Link: https://lore.kernel.org/r/20190809163334.489360-4-arnd@arndb.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-08-09 18:33:18 +02:00
dmaengine updates for v5.4-rc1 - Move Dmaengine DT bindings to YAML and convert Allwinner to schema. - FSL dma device_synchronize implementation - DW split acpi and of helpers and updates to driver and support for Elkhart Lake - Move filter fn as private for omap-dma and edma drivers and improvements to these drivers - Mark expected switch fall-through in couple of drivers - Renames of shdma and nbpfaxi binding document - Minor updates to bunch of drivers -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJdgKdzAAoJEHwUBw8lI4NHpS8P/R9goCZa+8gheQbgJKR7lyH0 a+6wTUA3z8bAw0Z8QiOtZkeYbSYUQSWYzPIjjOkpZXLLXvzHfDLBZ9LBEQORhPU6 hVC3RZ4hey/HFC1pyZcua6dniFIXicD/zIUvqeYTnC7gb+q7J2WgJaTub/OuZKL0 JQ45dDE219nkFWZ37wUJgAEWq2r429JoxkJwFUZeKKldpMy3pKRSCt+FPnDZZBtt n6DBSbWbzPZ6DtKGc6Sh75bFm12xHhuCS0uB6k7g3APY6T8NslpGTsFwtp5PB/Q0 5BLwLAZZjeya6RgPBne0cjZ75YFb+Rf+yLM5AErYPLZTy07/88BtMDWXSjJbDDlh BFu93hDqB/0rp28HJF9ZoH5MNp181cyvkQztt83gB97Lkk8wBGAyvqIExe2ZeHw6 XJibCDjS9A1xjxWi4IBx/YyiSOesrnWvRvFcCXnEcsRM74m2xX9oLC+dwQgx2o9f 92V5edxojDlKk8J2ZNX8meojIXx955/et6SgUC61S/hhpZAMnJgNfBJ0FtrR2q3Q qnpYsy1Ef9399laQGRzPQ2wgs6PRQfoNTZUa1evTQW3fBdoy+yF19tsVhVwhxXt8 LqKL6Y/fKlL7/wtdBQIeyJLp3CF1EyaePuZcaUnd/BM8ZKLetCT64iM6nJLjoZY9 xpYkmce5/u+65x0mQJ/B =Q8bz -----END PGP SIGNATURE----- Merge tag 'dmaengine-5.4-rc1' of git://git.infradead.org/users/vkoul/slave-dma Pull dmaengine updates from Vinod Koul: - Move Dmaengine DT bindings to YAML and convert Allwinner to schema. - FSL dma device_synchronize implementation - DW split acpi and of helpers and updates to driver and support for Elkhart Lake - Move filter fn as private for omap-dma and edma drivers and improvements to these drivers - Mark expected switch fall-through in couple of drivers - Renames of shdma and nbpfaxi binding document - Minor updates to bunch of drivers * tag 'dmaengine-5.4-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (55 commits) dmaengine: ti: edma: Use bitmap_set() instead of open coded edma_set_bits() dmaengine: ti: edma: Only reset region0 access registers dmaengine: ti: edma: Do not reset reserved paRAM slots dmaengine: iop-adma.c: fix printk format warning dmaengine: stm32-dma: Use struct_size() helper dt-bindings: dmaengine: dma-common: Fix the dma-channel-mask property dmanegine: ioat/dca: Use struct_size() helper dmaengine: iop-adma: remove set but not used variable 'slots_per_op' dmaengine: dmatest: Add support for completion polling dmaengine: ti: omap-dma: Remove variable override in omap_dma_tx_status() dmaengine: ti: omap-dma: Remove 'Assignment in if condition' dmaengine: ti: edma: Remove 'Assignment in if condition' dmaengine: dw: platform: Split OF helpers to separate module dmaengine: dw: platform: Split ACPI helpers to separate module dmaengine: dw: platform: Move handle check to dw_dma_acpi_controller_register() dmaengine: dw: platform: Switch to acpi_dma_controller_register() dmaengine: dw: platform: Use devm_platform_ioremap_resource() dmaengine: dw: platform: Enable iDMA 32-bit on Intel Elkhart Lake dmaengine: dw: platform: Use struct dw_dma_chip_pdata dmaengine: dw: Export struct dw_dma_chip_pdata for wider use ...
2019-09-17 19:04:40 -07:00
DMA: TXx9 Soc DMA Controller driver This patch adds support for the integrated DMAC of the TXx9 family. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-04-23 00:40:30 +09:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
DMA: TXx9 Soc DMA Controller driver This patch adds support for the integrated DMAC of the TXx9 family. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-04-23 00:40:30 +09:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
DMA: TXx9 Soc DMA Controller driver This patch adds support for the integrated DMAC of the TXx9 family. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-04-23 00:40:30 +09:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dma: tegra: add dmaengine based dma driver Add dmaengine based NVIDIA's Tegra APB DMA driver. This driver support the slave mode of data transfer from peripheral to memory and vice versa. The driver supports for the cyclic and non-cyclic mode of data transfer. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2012-06-06 10:55:27 +05:30
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dma: tegra: add dmaengine based dma driver Add dmaengine based NVIDIA's Tegra APB DMA driver. This driver support the slave mode of data transfer from peripheral to memory and vice versa. The driver supports for the cyclic and non-cyclic mode of data transfer. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2012-06-06 10:55:27 +05:30
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
Kconfig: Allow k3dma driver to be selected for more then HISI3xx platforms This allows the k3dma driver to be selected on HiKey via the ARCH_HISI dependency. Cc: Zhangfei Gao <zhangfei.gao@linaro.org> Cc: Jingoo Han <jg1.han@samsung.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Mark Brown <broonie@kernel.org> Cc: Andy Green <andy@warmcat.com> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-08-29 10:30:53 -07:00
dmaengine: add driver for Samsung s3c24xx SoCs This adds a new driver to support the s3c24xx dma using the dmaengine and makes the old one in mach-s3c24xx obsolete in the long run. Conceptually the s3c24xx-dma feels like a distant relative of the pl08x with numerous virtual channels being mapped to a lot less physical ones. The driver therefore borrows a lot from the amba-pl08x driver in this regard. Functionality-wise the driver gains a memcpy ability in addition to the slave_sg one. The driver supports both the method for requesting the peripheral used by SoCs before the S3C2443 and the different method for S3C2443 and later. On earlier SoCs the hardware channels usable for specific peripherals is constrainted while on later SoCs all channels can be used for any peripheral. Tested on a s3c2416-based board, memcpy using the dmatest module and slave_sg partially using the spi-s3c64xx driver. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-10-08 06:42:10 +09:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: add driver for Samsung s3c24xx SoCs This adds a new driver to support the s3c24xx dma using the dmaengine and makes the old one in mach-s3c24xx obsolete in the long run. Conceptually the s3c24xx-dma feels like a distant relative of the pl08x with numerous virtual channels being mapped to a lot less physical ones. The driver therefore borrows a lot from the amba-pl08x driver in this regard. Functionality-wise the driver gains a memcpy ability in addition to the slave_sg one. The driver supports both the method for requesting the peripheral used by SoCs before the S3C2443 and the different method for S3C2443 and later. On earlier SoCs the hardware channels usable for specific peripherals is constrainted while on later SoCs all channels can be used for any peripheral. Tested on a s3c2416-based board, memcpy using the dmatest module and slave_sg partially using the spi-s3c64xx driver. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-10-08 06:42:10 +09:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: sh: Add Support SuperH DMA Engine driver This supported all DMA channels, and it was tested in SH7722, SH7780, SH7785 and SH7763. This can not use with SH DMA API. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-09-07 03:26:23 +00:00
dmaengine: fsl-edma: add ColdFire mcf5441x edma support This patch adds support for ColdFire mcf5441x-family edma module. The ColdFire edma module is slightly different from fsl-edma, so a new driver is added. But most of the code is common between fsl-edma and mcf-edma so it has been collected into a separate common module fsl-edma-common (patch 1/3). Signed-off-by: Angelo Dureghello <angelo@sysam.it> Tested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-08-19 19:27:16 +02:00
dmaengine: milbeaut-hdmac: Add HDMAC driver for Milbeaut platforms Driver for Socionext Milbeaut HDMAC controller. The controller has upto 8 floating channels, that need a predefined slave-id to work from a set of slaves. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Link: https://lore.kernel.org/r/20191015033359.14925-1-jassisinghbrar@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-10-14 22:33:59 -05:00
dmaengine: milbeaut-xdmac: Add XDMAC driver for Milbeaut platforms Driver for Socionext Milbeaut XDMAC controller. The controller only supports Mem-To-Mem transfers over upto 8 configurable channels. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Link: https://lore.kernel.org/r/20191015033219.14713-1-jassisinghbrar@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-10-14 22:32:19 -05:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: mmp_pdma: enable COMPILE_TEST To get more coverage, enable COMPILE_TEST for this driver. Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-09-02 15:55:56 +05:30
Add COH 901 318 DMA block driver v5 This patch adds support for the ST-Ericsson COH 901 318 DMA block, found in the U300 series platforms. It registers a DMA slave for device I/O and also a memcpy slave for memcpy. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-11-19 19:49:17 +01:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
Add COH 901 318 DMA block driver v5 This patch adds support for the ST-Ericsson COH 901 318 DMA block, found in the U300 series platforms. It registers a DMA slave for device I/O and also a memcpy slave for memcpy. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-11-19 19:49:17 +01:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: mmp_tdma: enable COMPILE_TEST To get more coverage, enable COMPILE_TEST for this driver. While at it, to fix build on other archs, select MMP_SRAM only for ARCH_MMP and also fix the platform header Suggested-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-09-02 15:57:09 +05:30
DMAENGINE: Support for ST-Ericssons DMA40 block v3 This is a straightforward driver for the ST-Ericsson DMA40 DMA controller found in U8500, implemented akin to the existing COH 901 318 driver. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Srinidh Kasagar <srinidhi.kasagar@stericsson.com> Cc: STEricsson_nomadik_linux@list.st.com Cc: Alessandro Rubini <rubini@unipv.it> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-03-30 15:33:42 +02:00
dmaengine: mmp_tdma: enable COMPILE_TEST To get more coverage, enable COMPILE_TEST for this driver. While at it, to fix build on other archs, select MMP_SRAM only for ARCH_MMP and also fix the platform header Suggested-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-09-02 15:57:09 +05:30
dmaengine: mmp_tdma: add missing select GENERIC_ALLOCATOR in Kconfig There are some compilation errors when CONFIG_MMP_TDMA is enabled and CONFIG_GENERIC_ALLOCATOR is disabled: drivers/built-in.o: In function `mmp_tdma_prep_dma_cyclic': mmp_tdma.c:(.text+0x7890e): undefined reference to `gen_pool_dma_alloc' drivers/built-in.o: In function `mmp_tdma_free_chan_resources': mmp_tdma.c:(.text+0x78aca): undefined reference to `gen_pool_free' drivers/built-in.o: In function `mmp_tdma_probe': mmp_tdma.c:(.text+0x78ea8): undefined reference to `of_gen_pool_get' This commit fix this problem by selecting GENERIC_ALLOCATOR when CONFIG_MMP_TDMA is enabled. Signed-off-by: Jérémy Lefaure <jeremy.lefaure@lse.epita.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-10-06 17:59:53 -04:00
DMAENGINE: Support for ST-Ericssons DMA40 block v3 This is a straightforward driver for the ST-Ericsson DMA40 DMA controller found in U8500, implemented akin to the existing COH 901 318 driver. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Srinidh Kasagar <srinidhi.kasagar@stericsson.com> Cc: STEricsson_nomadik_linux@list.st.com Cc: Alessandro Rubini <rubini@unipv.it> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-03-30 15:33:42 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
DMAENGINE: Support for ST-Ericssons DMA40 block v3 This is a straightforward driver for the ST-Ericsson DMA40 DMA controller found in U8500, implemented akin to the existing COH 901 318 driver. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Srinidh Kasagar <srinidhi.kasagar@stericsson.com> Cc: STEricsson_nomadik_linux@list.st.com Cc: Alessandro Rubini <rubini@unipv.it> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-03-30 15:33:42 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
ppc440spe-adma: adds updated ppc440spe adma driver This patch adds new version of the PPC440SPe ADMA driver. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-12-11 21:24:44 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
ppc440spe-adma: adds updated ppc440spe adma driver This patch adds new version of the PPC440SPe ADMA driver. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-12-11 21:24:44 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
ppc440spe-adma: adds updated ppc440spe adma driver This patch adds new version of the PPC440SPe ADMA driver. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-12-11 21:24:44 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dma: Add timb-dma Adds the support for the DMA engine withing the timberdale FPGA. The DMA channels are strict device to host, or host to device and can not be used for generic memcpy. Signed-off-by: Richard Röjfors <richard.rojfors@pelagicore.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-03-25 19:44:21 +01:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dma: Add timb-dma Adds the support for the DMA engine withing the timberdale FPGA. The DMA channels are strict device to host, or host to device and can not be used for generic memcpy. Signed-off-by: Richard Röjfors <richard.rojfors@pelagicore.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-03-25 19:44:21 +01:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: mv_xor: Allow selecting mv_xor for mvebu only compatible SoC Armada 3700 SoC uses the mv_xor driver but don't select anymore the PLAT_ORION symbol. This commit extends the dependency of the mv_xor driver to the more modern SoCs only compatible with ARCH_MVEBU, which allows using it with the Armada 3700 SoC. In the same time it also add the COMPILE_TEST dependency allowing a wider test coverage. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-29 09:49:08 +02:00
dmaengine: add CSR SiRFprimaII DMAC driver Cc: Jassi Brar <jaswinder.singh@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> [fixed direction enums and cyclic api based on changes already merged] Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2011-10-27 19:22:39 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: add CSR SiRFprimaII DMAC driver Cc: Jassi Brar <jaswinder.singh@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> [fixed direction enums and cyclic api based on changes already merged] Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2011-10-27 19:22:39 -07:00
dmaengine: mv_xor_v2: new driver The new mv_xor_v2 driver supports the XOR engines found in the 64-bits ARM from Marvell of the Armada 7K and Armada 8K family. This XOR engine is a completely new hardware block, entirely different from the one used on previous Marvell Armada platforms, which use the existing mv_xor driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-16 14:28:34 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: Kconfig: Extend the dependency for MXS_DMA Currently it is not possible to select the mxs dma driver when only mx6sx or mx7 are selected. Extend the dependency to allow the mxs dma driver to be built whenever ARCH_MXS or ARCH_MXC is selected. This has the benefit to avoid having to add new entries in the MXS_DMA Kconfig everytime a new i.MX SoC shows up and it also makes it consistent with the other i.MX DMA engines, such as IMX_DMA and IMX_SDMA. While at it, also pass COMPILE_TEST for increasing the build coverage. Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-06-08 19:46:23 -03:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: add CSR SiRFprimaII DMAC driver Cc: Jassi Brar <jaswinder.singh@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> [fixed direction enums and cyclic api based on changes already merged] Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2011-10-27 19:22:39 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: Kconfig: Simplify the help text for MXS_DMA Currently the help text for the MXS_DMA option is incomplete as it does not mention MX6SX, MX6ULL and MX7D, for example. Instead of extending this list everytime a new SoC comes out, let's keep the text more generic. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-06-16 11:58:46 -03:00
dmaengine: add CSR SiRFprimaII DMAC driver Cc: Jassi Brar <jaswinder.singh@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> [fixed direction enums and cyclic api based on changes already merged] Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2011-10-27 19:22:39 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: add TI EDMA DMA engine driver Add a DMA engine driver for the TI EDMA controller. This driver is implemented as a wrapper around the existing DaVinci private DMA implementation. This approach allows for incremental conversion of each peripheral driver to the DMA engine API. The EDMA driver supports slave transfers but does not yet support cyclic transfers. Signed-off-by: Matt Porter <mporter@ti.com> Tested-by: Tom Rini <trini@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2012-08-22 21:09:34 -04:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: add TI EDMA DMA engine driver Add a DMA engine driver for the TI EDMA controller. This driver is implemented as a wrapper around the existing DaVinci private DMA implementation. This approach allows for incremental conversion of each peripheral driver to the DMA engine API. The EDMA driver supports slave transfers but does not yet support cyclic transfers. Signed-off-by: Matt Porter <mporter@ti.com> Tested-by: Tom Rini <trini@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2012-08-22 21:09:34 -04:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: Add driver for TI DMA crossbar on DRA7x The DRA7x has more peripherals with DMA requests than the sDMA can handle: 205 vs 127. All DMA requests are routed through the DMA crossbar, which can be configured to route selected incoming DMA requests to specific sDMA request. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-04-09 12:35:49 +03:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
ppc440spe-adma: adds updated ppc440spe adma driver This patch adds new version of the PPC440SPe ADMA driver. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-12-11 21:24:44 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
DMA: PL330: Add dma api driver Add DMA Engine API driver for the PL330 DMAC. This driver is supposed to be reusable by various platforms that have one or more PL330 DMACs. Atm, DMA_SLAVE and DMA_MEMCPY capabilities have been implemented. Signed-off-by: Jassi Brar <jassi.brar@samsung.com> Reviewed-by: Linus Walleij <linus.walleij@stericsson.com> [dan.j.williams@intel.com: missing slab.h and ->device_control() fixups] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-05-23 20:28:19 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
DMA: PL330: Add dma api driver Add DMA Engine API driver for the PL330 DMAC. This driver is supposed to be reusable by various platforms that have one or more PL330 DMACs. Atm, DMA_SLAVE and DMA_MEMCPY capabilities have been implemented. Signed-off-by: Jassi Brar <jassi.brar@samsung.com> Reviewed-by: Linus Walleij <linus.walleij@stericsson.com> [dan.j.williams@intel.com: missing slab.h and ->device_control() fixups] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-05-23 20:28:19 -07:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
DMA: PL330: Add dma api driver Add DMA Engine API driver for the PL330 DMAC. This driver is supposed to be reusable by various platforms that have one or more PL330 DMACs. Atm, DMA_SLAVE and DMA_MEMCPY capabilities have been implemented. Signed-off-by: Jassi Brar <jassi.brar@samsung.com> Reviewed-by: Linus Walleij <linus.walleij@stericsson.com> [dan.j.williams@intel.com: missing slab.h and ->device_control() fixups] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-05-23 20:28:19 -07:00
dmaengine: Add Actions Semi Owl family S900 DMA driver Add Actions Semi Owl family S900 DMA driver. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-26 10:36:57 +05:30
dmaengine: Driver for Topcliff PCH DMA controller Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platforms. This adds the driver for Topcliff PCH DMA controller. The DMA channels are strictly for device to host or host to device transfers and cannot be used for generic memcpy. Signed-off-by: Yong Wang <yong.y.wang@intel.com> [kill GFP_ATOMIC, kill __raw_{read|write}l, locking fixlet] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-07-30 16:23:03 +08:00
pch_dma: Support new device LAPIS Semiconductor ML7831 IOH ML7831 is companion chip for Intel Atom E6xx series. Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2011-11-17 16:14:23 +09:00
dma: pch_dma: Fix Kconfig dependencies The pch_dma driver is for a companion chip to the Intel Atom E600 series processors. These are 32-bit x86 processors so the driver is only needed on X86_32. Add COMPILE_TEST as an alternative, so that the driver can still be build-tested elsewhere. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-05-16 16:17:37 +02:00
dmaengine: Driver for Topcliff PCH DMA controller Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platforms. This adds the driver for Topcliff PCH DMA controller. The DMA channels are strictly for device to host or host to device transfers and cannot be used for generic memcpy. Signed-off-by: Yong Wang <yong.y.wang@intel.com> [kill GFP_ATOMIC, kill __raw_{read|write}l, locking fixlet] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-07-30 16:23:03 +08:00
pch_dma: support new device ML7213 IOH Support new device OKI SEMICONDUCTOR's ML7213 IOH(Input/Output Hub) which is for IVI(In-Vehicle Infotainment) use. The ML7213 is companion chip for Intel Atom E6xx series. The ML7213 is completely compatible for Intel EG20T PCH. Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2011-01-05 17:43:52 +09:00
pch_dma: Change company name OKI SEMICONDUCTOR to LAPIS Semiconductor On October 1 in 2011, OKI SEMICONDUCTOR Co., Ltd. changed the company name in to LAPIS Semiconductor Co., Ltd. Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2011-11-17 16:14:22 +09:00
pch_dma: Support new device LAPIS Semiconductor ML7831 IOH ML7831 is companion chip for Intel Atom E6xx series. Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2011-11-17 16:14:23 +09:00
dmaengine: Driver for Topcliff PCH DMA controller Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platforms. This adds the driver for Topcliff PCH DMA controller. The DMA channels are strictly for device to host or host to device transfers and cannot be used for generic memcpy. Signed-off-by: Yong Wang <yong.y.wang@intel.com> [kill GFP_ATOMIC, kill __raw_{read|write}l, locking fixlet] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-07-30 16:23:03 +08:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: Add Freescale i.MX SDMA support This patch adds support for the Freescale i.MX SDMA engine. The SDMA engine is a scatter/gather DMA engine which is implemented as a seperate coprocessor. SDMA needs its own firmware which is requested using the standard request_firmware mechanism. The firmware has different entry points for each peripheral type, so drivers have to pass the peripheral type to the DMA engine which in turn picks the correct firmware entry point from a table contained in the firmware image itself. The original Freescale code also supports support for transfering data to the internal SRAM which needs different entry points to the firmware. Support for this is currently not implemented. Also, support for the ASRC (asymmetric sample rate converter) is skipped. I took a very simple approach to implement dmaengine support. Only a single descriptor is statically assigned to a each channel. This means that transfers can't be queued up but only a single transfer is in progress. This simplifies implementation a lot and is sufficient for the usual device/memory transfers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Linus Walleij <linus.ml.walleij@gmail.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-09-30 13:56:34 +00:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: Add Freescale i.MX SDMA support This patch adds support for the Freescale i.MX SDMA engine. The SDMA engine is a scatter/gather DMA engine which is implemented as a seperate coprocessor. SDMA needs its own firmware which is requested using the standard request_firmware mechanism. The firmware has different entry points for each peripheral type, so drivers have to pass the peripheral type to the DMA engine which in turn picks the correct firmware entry point from a table contained in the firmware image itself. The original Freescale code also supports support for transfering data to the internal SRAM which needs different entry points to the firmware. Support for this is currently not implemented. Also, support for the ASRC (asymmetric sample rate converter) is skipped. I took a very simple approach to implement dmaengine support. Only a single descriptor is statically assigned to a each channel. This means that transfers can't be queued up but only a single transfer is in progress. This simplifies implementation a lot and is sufficient for the usual device/memory transfers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Linus Walleij <linus.ml.walleij@gmail.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-09-30 13:56:34 +00:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: Add Freescale i.MX SDMA support This patch adds support for the Freescale i.MX SDMA engine. The SDMA engine is a scatter/gather DMA engine which is implemented as a seperate coprocessor. SDMA needs its own firmware which is requested using the standard request_firmware mechanism. The firmware has different entry points for each peripheral type, so drivers have to pass the peripheral type to the DMA engine which in turn picks the correct firmware entry point from a table contained in the firmware image itself. The original Freescale code also supports support for transfering data to the internal SRAM which needs different entry points to the firmware. Support for this is currently not implemented. Also, support for the ASRC (asymmetric sample rate converter) is skipped. I took a very simple approach to implement dmaengine support. Only a single descriptor is statically assigned to a each channel. This means that transfers can't be queued up but only a single transfer is in progress. This simplifies implementation a lot and is sufficient for the usual device/memory transfers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Linus Walleij <linus.ml.walleij@gmail.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-09-30 13:56:34 +00:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: Add Freescale i.MX1/21/27 DMA driver This driver is currently implemented as a user to the old i.MX DMA API. This allows us to convert each user of the old API to the dmaengine API one by one. Once this is done the old DMA driver can be merged into the i.MX dmaengine driver. V2: remove some debug leftovers and unused variables Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-10-06 10:25:55 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: Add Freescale i.MX1/21/27 DMA driver This driver is currently implemented as a user to the old i.MX DMA API. This allows us to convert each user of the old API to the dmaengine API one by one. Once this is done the old DMA driver can be merged into the i.MX dmaengine driver. V2: remove some debug leftovers and unused variables Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-10-06 10:25:55 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: Add Freescale i.MX1/21/27 DMA driver This driver is currently implemented as a user to the old i.MX DMA API. This allows us to convert each user of the old API to the dmaengine API one by one. Once this is done the old DMA driver can be merged into the i.MX dmaengine driver. V2: remove some debug leftovers and unused variables Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-10-06 10:25:55 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: mxs-dma: add dma support for i.MX23/28 This patch adds dma support for Freescale MXS-based SoC i.MX23/28, including apbh-dma and apbx-dma. * apbh-dma and apbx-dma are supported in the driver as two mxs-dma instances. * apbh-dma is different between mx23 and mx28, hardware version register is used to differentiate. * mxs-dma supports pio function besides data transfer. The driver uses dma_data_direction DMA_NONE to identify the pio mode, and steals sgl and sg_len to get pio words and numbers from clients. * mxs dmaengine has some very specific features, like sense function and the special NAND support (nand_lock, nand_wait4ready). These are too specific to implemented in generic dmaengine driver. * The driver refers to imx-sdma and only a single descriptor is statically assigned to each channel. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2011-02-27 00:47:42 +08:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: mxs-dma: add dma support for i.MX23/28 This patch adds dma support for Freescale MXS-based SoC i.MX23/28, including apbh-dma and apbx-dma. * apbh-dma and apbx-dma are supported in the driver as two mxs-dma instances. * apbh-dma is different between mx23 and mx28, hardware version register is used to differentiate. * mxs-dma supports pio function besides data transfer. The driver uses dma_data_direction DMA_NONE to identify the pio mode, and steals sgl and sg_len to get pio words and numbers from clients. * mxs dmaengine has some very specific features, like sense function and the special NAND support (nand_lock, nand_wait4ready). These are too specific to implemented in generic dmaengine driver. * The driver refers to imx-sdma and only a single descriptor is statically assigned to each channel. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2011-02-27 00:47:42 +08:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: add ep93xx DMA support The ep93xx DMA controller has 10 independent memory to peripheral (M2P) channels, and 2 dedicated memory to memory (M2M) channels. M2M channels can also be used by SPI and IDE to perform DMA transfers to/from their memory mapped FIFOs. This driver supports both M2P and M2M channels with DMA_SLAVE, DMA_CYCLIC and DMA_MEMCPY (M2M only) capabilities. Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi> Signed-off-by: Ryan Mallon <rmallon@gmail.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-05-29 13:10:02 +03:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: add ep93xx DMA support The ep93xx DMA controller has 10 independent memory to peripheral (M2P) channels, and 2 dedicated memory to memory (M2M) channels. M2M channels can also be used by SPI and IDE to perform DMA transfers to/from their memory mapped FIFOs. This driver supports both M2P and M2M channels with DMA_SLAVE, DMA_CYCLIC and DMA_MEMCPY (M2M only) capabilities. Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi> Signed-off-by: Ryan Mallon <rmallon@gmail.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-05-29 13:10:02 +03:00
dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support This patch adds support for the Flexible Direct Memory Access (FDMA) core driver. The FDMA is a slim core CPU with a dedicated firmware. It is a general purpose DMA controller capable of supporting 16 independent DMA channels. Data moves maybe from memory to memory or between memory and paced latency critical real time targets and it is found on al STi based chipsets. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-10-18 10:39:11 +01:00
dmaengine: st_fdma: Revert: "Revert: Update st_fdma to 'depends on REMOTEPROC'" This reverts commit 6d066389d598b3c3818c3c841179c2f95bbfe702 "(dmaengine: st_fdma: Revert: Update st_fdma to 'depends on REMOTEPROC')" as the commit it reverted was fine. Reported-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-11-17 15:23:01 +05:30
dmaengine: st_fdma: Add STMicroelectronics FDMA engine driver support This patch adds support for the Flexible Direct Memory Access (FDMA) core driver. The FDMA is a slim core CPU with a dedicated firmware. It is a general purpose DMA controller capable of supporting 16 independent DMA channels. Data moves maybe from memory to memory or between memory and paced latency critical real time targets and it is found on al STi based chipsets. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-10-18 10:39:11 +01:00
dmaengine: Add STM32 DMA driver This patch adds support for the STM32 DMA controller. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-16 15:59:14 +02:00
dmaengine: stm32-dma: enable COMPILE_TEST To get more coverage, enable COMPILE_TEST for this driver. Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-09-02 15:57:51 +05:30
dmaengine: Add STM32 DMA driver This patch adds support for the STM32 DMA controller. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-16 15:59:14 +02:00
dmaengine: stm32-dma: Fix typo in Kconfig As STM32 DMA driver is only used as buit-in driver, it couldn't be used as module. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Reviewed-by: Ludovic BARRE <ludovic.barre@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-12-13 14:40:44 +01:00
dmaengine: Add STM32 DMA driver This patch adds support for the STM32 DMA controller. Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-10-16 15:59:14 +02:00
dmaengine: Add STM32 DMAMUX driver This patch implements the STM32 DMAMUX driver. The DMAMUX request multiplexer allows routing a DMA request line between the peripherals and the DMA controllers of the product. The routing function is ensured by a programmable multi-channel DMA request line multiplexer. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs. The DMAMUX may also be used as a DMA request generator from programmable events on its input trigger signals Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-22 09:31:30 +02:00
dmaengine: Add STM32 MDMA driver This patch adds the driver for the STM32 MDMA controller. Master Direct memory access (MDMA) is used in order to provide high-speed data transfer between memory and memory or between peripherals and memory. MDMA controller provides a master AXI interface for main memory and peripheral registers access (system access port) and a master AHB interface only for Cortex-M7 TCM memory access (TCM access port). MDMA works in conjunction with the standard DMA controllers (DMA1 or DMA2). It offers up to 64 channels, each dedicated to managing memory access requests from one of the DMA stream memory buffer or other peripherals (w/ integrated FIFO). Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-28 17:36:41 +02:00
dmaengine: stm32_mdma: add CONFIG_OF dependency Without CONFIG_OF we get a build warning: warning: (STM32_MDMA) selects DMA_OF which has unmet direct dependencies (DMADEVICES && OF) This adds a dependency on CONFIG_OF. Since this means we no longer need to select 'DMA_OF', I'm dropping that line as well. Fixes: a4ffb13c8946 ("dmaengine: Add STM32 MDMA driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-10-11 16:00:04 +02:00
dmaengine: Add STM32 MDMA driver This patch adds the driver for the STM32 MDMA controller. Master Direct memory access (MDMA) is used in order to provide high-speed data transfer between memory and memory or between peripherals and memory. MDMA controller provides a master AXI interface for main memory and peripheral registers access (system access port) and a master AHB interface only for Cortex-M7 TCM memory access (TCM access port). MDMA works in conjunction with the standard DMA controllers (DMA1 or DMA2). It offers up to 64 channels, each dedicated to managing memory access requests from one of the DMA stream memory buffer or other peripherals (w/ integrated FIFO). Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-28 17:36:41 +02:00
dmaengine: sprd: Add Spreadtrum DMA driver This patch adds the DMA controller driver for Spreadtrum SC9860 platform. Signed-off-by: Baolin Wang <baolin.wang@spreadtrum.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-10-24 13:47:50 +08:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
ASoC: samsung: pass filter function as pointer As we are now passing the filter data as pointers to the drivers, we can take the final step and also pass the filter function the same way. I'm keeping this change separate, as there it's less obvious that this is a net win. Upsides of this are: - The ASoC drivers are completely independent from the DMA engine implementation, which simplifies the Kconfig logic and in theory allows the same sound drivers to be built in a kernel that supports different kinds of dmaengine drivers. - Consistency with other subsystems and drivers On the other hand, we have a few downsides: - The s3c24xx-dma driver now needs to be built-in for the ac97 platform device to be instantiated on s3c2440. - samsung_dmaengine_pcm_config cannot be marked 'const' any more because the filter function pointer needs to be set at runtime. This is safe as long we don't have multiple different DMA engines in thet same system at runtime, but is nonetheless ugly. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-11-18 22:31:11 +01:00
dmaengine: s3c24xx: enable COMPILE_TEST To get more coverage, enable COMPILE_TEST for this driver. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-09-02 16:00:41 +05:30
DMA: sa11x0: add SA-11x0 DMA driver Add support for the SA-11x0 DMA driver, which replaces the private API version in arch/arm/mach-sa1100/dma.c. We model this as a set of virtual DMA channels, one for each request signal, and assign the virtual DMA channel to a physical DMA channel when there is work to be done. This allows DMA users to claim their channels, and hold them while not in use, without affecting the availability of the physical channels. Another advantage over this approach, compared to the private version, is that a channel can be reconfigured on the fly without having to release and re-request it - which for the IrDA driver, allows us to use DMA for SIR mode transmit without eating up three physical channels. As IrDA is half-duplex, we actually only need one physical channel, and this architecture allows us to achieve that. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-09 21:44:07 +00:00
dmaengine: split out virtual channel DMA support from sa11x0 driver Split the virtual slave channel DMA support from the sa11x0 driver so this code can be shared with other slave DMA engine drivers. Acked-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-04-13 12:07:23 +01:00
DMA: sa11x0: add SA-11x0 DMA driver Add support for the SA-11x0 DMA driver, which replaces the private API version in arch/arm/mach-sa1100/dma.c. We model this as a set of virtual DMA channels, one for each request signal, and assign the virtual DMA channel to a physical DMA channel when there is work to be done. This allows DMA users to claim their channels, and hold them while not in use, without affecting the availability of the physical channels. Another advantage over this approach, compared to the private version, is that a channel can be reconfigured on the fly without having to release and re-request it - which for the IrDA driver, allows us to use DMA for SIR mode transmit without eating up three physical channels. As IrDA is half-duplex, we actually only need one physical channel, and this architecture allows us to achieve that. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-09 21:44:07 +00:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
DMA: sa11x0: add SA-11x0 DMA driver Add support for the SA-11x0 DMA driver, which replaces the private API version in arch/arm/mach-sa1100/dma.c. We model this as a set of virtual DMA channels, one for each request signal, and assign the virtual DMA channel to a physical DMA channel when there is work to be done. This allows DMA users to claim their channels, and hold them while not in use, without affecting the availability of the physical channels. Another advantage over this approach, compared to the private version, is that a channel can be reconfigured on the fly without having to release and re-request it - which for the IrDA driver, allows us to use DMA for SIR mode transmit without eating up three physical channels. As IrDA is half-duplex, we actually only need one physical channel, and this architecture allows us to achieve that. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-01-09 21:44:07 +00:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: mmp_tdma: add mmp tdma support Add support for two-channel dma under dmaengine support: mmp-adma and pxa910-squ Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Leo Yan <leoy@marvell.com> Signed-off-by: Qiao Zhou <zhouqiao@marvell.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2012-06-15 11:04:08 +08:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: mmp_tdma: add mmp tdma support Add support for two-channel dma under dmaengine support: mmp-adma and pxa910-squ Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Leo Yan <leoy@marvell.com> Signed-off-by: Qiao Zhou <zhouqiao@marvell.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
2012-06-15 11:04:08 +08:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: add OMAP DMA engine driver Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-04-13 12:10:24 +01:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: add OMAP DMA engine driver Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-04-13 12:10:24 +01:00
dmaengine: tegra-adma: Add support for Tegra210 ADMA Add support for the Tegra210 Audio DMA controller that is used for transferring data between system memory and the Audio sub-system. The driver only supports cyclic transfers because this is being solely used for audio. This driver is based upon the work by Dara Ramesh <dramesh@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-12 18:02:23 +01:00
dmaengine: tegra210-adma: convert TEGRA210_ADMA from bool to tristate This driver currently uses modular infrastructure but is controlled by a bool Kconfig. There is a general consensus from the DMA reviewers and maintainers that "if it can be modular, it should be modular" in order to keep the bzImage size under control for multi platform kernels. Build tested only. Also needed some new pm_clk symbols exported before this commit is applied to tree in order to avoid modpost errors like: ERROR: "pm_clk_add_clk" [drivers/dma/tegra210-adma.ko] undefined! ERROR: "pm_clk_create" [drivers/dma/tegra210-adma.ko] undefined! ERROR: "pm_clk_destroy" [drivers/dma/tegra210-adma.ko] undefined! ERROR: "pm_clk_suspend" [drivers/dma/tegra210-adma.ko] undefined! ERROR: "pm_clk_resume" [drivers/dma/tegra210-adma.ko] undefined! These were added as exports in the v4.8-rc1 merge window. Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Jon Hunter <jonathanh@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: dmaengine@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-10-22 18:25:10 -04:00
dmaengine: tegra210-adma: remove PM_CLK dependency Tegra ADMA does not use pm-clk interface now and hence the dependency is removed from Kconfig. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-06-20 21:24:19 +05:30
dmaengine: tegra-adma: Add support for Tegra210 ADMA Add support for the Tegra210 Audio DMA controller that is used for transferring data between system memory and the Audio sub-system. The driver only supports cyclic transfers because this is being solely used for audio. This driver is based upon the work by Dara Ramesh <dramesh@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-12 18:02:23 +01:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: timb-dma: enable COMPILE_TEST To get more coverage, enable COMPILE_TEST for this driver. Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-09-02 16:07:05 +05:30
dmaengine: Add support for BCM2835 Add support for DMA controller of BCM2835 as used in the Raspberry Pi. Currently it only supports cyclic DMA. Signed-off-by: Florian Meier <florian.meier@koalo.de> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-01-06 20:18:24 +01:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: Add support for BCM2835 Add support for DMA controller of BCM2835 as used in the Raspberry Pi. Currently it only supports cyclic DMA. Signed-off-by: Florian Meier <florian.meier@koalo.de> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-01-06 20:18:24 +01:00
dmaengine: uniphier-mdmac: add UniPhier MIO DMAC driver The MIO DMAC (Media IO DMA Controller) is used in UniPhier LD4, Pro4, and sLD8 SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-10-12 01:41:03 +09:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dma: Add Freescale eDMA engine driver support Add Freescale enhanced direct memory(eDMA) controller support. This module can be found on Vybrid and LS-1 SoCs. Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Jingchang Lu <b35083@freescale.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-02-18 10:17:12 +08:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dma: Add Freescale eDMA engine driver support Add Freescale enhanced direct memory(eDMA) controller support. This module can be found on Vybrid and LS-1 SoCs. Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Jingchang Lu <b35083@freescale.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-02-18 10:17:12 +08:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: Add MOXA ART DMA engine driver The MOXA ART SoC has a DMA controller capable of offloading expensive memory operations, such as large copies. This patch adds support for the controller including four channels. Two of these are used to handle MMC copy on the UC-7112-LX hardware. The remaining two can be used in a future audio driver or client application. Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-01-17 09:46:05 +01:00
dmaengine: xilinx: Rename driver and config In the existing vdma driver support for AXI DMA and CDMA got added so the driver is no longer VDMA specific. This patch renames the driver and DT binding doc to xilinx_dma and updates the Kconfig description for all the DMAS. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-24 10:51:25 +05:30
dmaengine: vdma: Add 64 bit addressing support to the driver This VDMA is a soft ip, which can be programmed to support 32 bit addressing or greater than 32 bit addressing. When the VDMA ip is configured for 32 bit address space the buffer address is specified by a single register (0x5C for MM2S and 0xAC for S2MM channel). When the VDMA core is configured for an address space greater than 32 then each buffer address is specified by a combination of two registers. The first register specifies the LSB 32 bits of address, while the next register specifies the MSB 32 bits of address. For example, 5Ch will specify the LSB 32 bits while 60h will specify the MSB 32 bits of the first start address. So we need to program two registers at a time. This patch adds the 64 bit addressing support to the vdma driver. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-06 10:38:08 +05:30
dma: Add Xilinx AXI Video Direct Memory Access Engine driver support This is the driver for the AXI Video Direct Memory Access (AXI VDMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type video target peripherals. The core provides efficient two dimensional DMA operations with independent asynchronous read and write channel operation. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Reviewed-by: Levente Kurusa <levex@linux.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-04-23 20:23:26 +05:30
dmaengine: xilinx: Rename driver and config In the existing vdma driver support for AXI DMA and CDMA got added so the driver is no longer VDMA specific. This patch renames the driver and DT binding doc to xilinx_dma and updates the Kconfig description for all the DMAS. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-24 10:51:25 +05:30
dma: Add Xilinx AXI Video Direct Memory Access Engine driver support This is the driver for the AXI Video Direct Memory Access (AXI VDMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type video target peripherals. The core provides efficient two dimensional DMA operations with independent asynchronous read and write channel operation. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Reviewed-by: Levente Kurusa <levex@linux.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-04-23 20:23:26 +05:30
dmaengine: xilinx: Rename driver and config In the existing vdma driver support for AXI DMA and CDMA got added so the driver is no longer VDMA specific. This patch renames the driver and DT binding doc to xilinx_dma and updates the Kconfig description for all the DMAS. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-24 10:51:25 +05:30
dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support Add support for AXI Multichannel Direct Memory Access (AXI MCDMA) core, which is a soft Xilinx IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides scatter-gather interface with multiple independent transmit and receive channels. The driver supports device_prep_slave_sg slave transfer mode. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1571763622-29281-7-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-10-22 22:30:22 +05:30
dma: Add Xilinx AXI Video Direct Memory Access Engine driver support This is the driver for the AXI Video Direct Memory Access (AXI VDMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type video target peripherals. The core provides efficient two dimensional DMA operations with independent asynchronous read and write channel operation. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Reviewed-by: Levente Kurusa <levex@linux.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-04-23 20:23:26 +05:30
dmaengine: Add Xilinx zynqmp dma engine driver support Added the driver for zynqmp dma engine used in Zynq UltraScale+ MPSoC. This dma controller supports memory to memory and I/O to I/O buffer transfers. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-01 17:07:06 +05:30
dma: Add Xilinx AXI Video Direct Memory Access Engine driver support This is the driver for the AXI Video Direct Memory Access (AXI VDMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type video target peripherals. The core provides efficient two dimensional DMA operations with independent asynchronous read and write channel operation. This module works on Zynq (ARM Based SoC) and Microblaze platforms. Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Reviewed-by: Levente Kurusa <levex@linux.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-04-23 20:23:26 +05:30
dmaengine: zxdma: Support ZTE ZX296702 dma Add ZTE ZX296702 dma controller support. Only device tree probe is support currently. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-05 22:06:08 +08:00
dmaengine: zx: rename zx296702_dma.c to zx_dma.c ZTE ZX dma driver is not ZX296702 specific. It works for not only ZX296702 but also other ZTE ZX family platforms like ZX296718. Let's rename the file to reflect that. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-12-15 22:03:35 +08:00
dmaengine: zxdma: enable COMPILE_TEST To get more coverage, enable COMPILE_TEST for this driver. Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-09-02 16:10:07 +05:30
dmaengine: Add driver for IMG MDC Add support for the IMG Multi-threaded DMA Controller (MDC) found on certain IMG SoCs. Currently this driver supports the variant present on the MIPS-based Pistachio SoC. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-12-11 14:59:17 -08:00
dmaengine: zx: rename zx296702_dma.c to zx_dma.c ZTE ZX dma driver is not ZX296702 specific. It works for not only ZX296702 but also other ZTE ZX family platforms like ZX296718. Let's rename the file to reflect that. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-12-15 22:03:35 +08:00
dmaengine: Add driver for IMG MDC Add support for the IMG Multi-threaded DMA Controller (MDC) found on certain IMG SoCs. Currently this driver supports the variant present on the MIPS-based Pistachio SoC. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-12-11 14:59:17 -08:00
dmaengine: Add support for APM X-Gene SoC DMA engine driver This patch implements the APM X-Gene SoC DMA engine driver. The APM X-Gene SoC DMA engine consists of 4 DMA channels for performing DMA operations. These DMA operations include memory copy, scatter-gather memory copy, raid5 xor, and raid6 p+q offloading. Signed-off-by: Rameshwar Prasad Sahu <rsahu@apm.com> Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-03-18 19:17:34 +05:30
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
[I/OAT]: DMA memcpy subsystem Provides an API for offloading memory copies to DMA devices Signed-off-by: Chris Leech <christopher.leech@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-05-23 17:18:44 -07:00
dmaengine: mediatek: Add MediaTek High-Speed DMA controller for MT7622 and MT7623 SoC MediaTek High-Speed DMA controller (HSDMA) on MT7622 and MT7623 SoC has a single ring is dedicated to memory-to-memory transfer through ring based descriptor management. Even though there is only one physical ring available inside HSDMA, the driver can be easily extended to the support of multiple virtual channels processing simultaneously by means of DMA_VIRTUAL_CHANNELS effort. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Fengguang Wu <fengguang.wu@intel.com> Cc: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2018-03-15 15:40:36 +08:00
dmaengine: qcom_bam_dma: move to qcom directory Creating a QCOM directory for all QCOM DMA source files. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Reviewed-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-02-04 23:34:32 -05:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: split out virtual channel DMA support from sa11x0 driver Split the virtual slave channel DMA support from the sa11x0 driver so this code can be shared with other slave DMA engine drivers. Acked-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-04-13 12:07:23 +01:00
dmaengine: Add Synopsys eDMA IP core driver Add Synopsys PCIe Endpoint eDMA IP core driver to kernel. This IP is generally distributed with Synopsys PCIe Endpoint IP (depends of the use and licensing agreement). This core driver, initializes and configures the eDMA IP using vma-helpers functions and dma-engine subsystem. This driver can be compile as built-in or external module in kernel. To enable this driver just select DW_EDMA option in kernel configuration, however it requires and selects automatically DMA_ENGINE and DMA_VIRTUAL_CHANNELS option too. In order to transfer data from point A to B as fast as possible this IP requires a dedicated memory space containing linked list of elements. All elements of this linked list are continuous and each one describes a data transfer (source and destination addresses, length and a control variable). For the sake of simplicity, lets assume a memory space for channel write 0 which allows about 42 elements. +---------+ | Desc #0 |-+ +---------+ | V +----------+ | Chunk #0 |-+ | CB = 1 | | +----------+ +-----+ +-----------+ +-----+ +----------+ +->| Burst #0 |->| ... |->| Burst #41 |->| llp | | +----------+ +-----+ +-----------+ +-----+ V +----------+ | Chunk #1 |-+ | CB = 0 | | +-----------+ +-----+ +-----------+ +-----+ +----------+ +->| Burst #42 |->| ... |->| Burst #83 |->| llp | | +-----------+ +-----+ +-----------+ +-----+ V +----------+ | Chunk #2 |-+ | CB = 1 | | +-----------+ +-----+ +------------+ +-----+ +----------+ +->| Burst #84 |->| ... |->| Burst #125 |->| llp | | +-----------+ +-----+ +------------+ +-----+ V +----------+ | Chunk #3 |-+ | CB = 0 | | +------------+ +-----+ +------------+ +-----+ +----------+ +->| Burst #126 |->| ... |->| Burst #129 |->| llp | +------------+ +-----+ +------------+ +-----+ Legend: - Linked list, also know as Chunk - Linked list element*, also know as Burst *CB*, also know as Change Bit, it's a control bit (and typically is toggled) that allows to easily identify and differentiate between the current linked list and the previous or the next one. - LLP, is a special element that indicates the end of the linked list element stream also informs that the next CB should be toggle On every last Burst of the Chunk (Burst #41, Burst #83, Burst #125 or even Burst #129) is set some flags on their control variable (RIE and LIE bits) that will trigger the send of "done" interruption. On the interruptions callback, is decided whether to recycle the linked list memory space by writing a new set of Bursts elements (if still exists Chunks to transfer) or is considered completed (if there is no Chunks available to transfer). On scatter-gather transfer mode, the client will submit a scatter-gather list of n (on this case 130) elements, that will be divide in multiple Chunks, each Chunk will have (on this case 42) a limited number of Bursts and after transferring all Bursts, an interrupt will be triggered, which will allow to recycle the all linked list dedicated memory again with the new information relative to the next Chunk and respective Burst associated and repeat the whole cycle again. On cyclic transfer mode, the client will submit a buffer pointer, length of it and number of repetitions, in this case each burst will correspond directly to each repetition. Each Burst can describes a data transfer from point A(source) to point B(destination) with a length that can be from 1 byte up to 4 GB. Since dedicated the memory space where the linked list will reside is limited, the whole n burst elements will be organized in several Chunks, that will be used later to recycle the dedicated memory space to initiate a new sequence of data transfers. The whole transfer is considered has completed when it was transferred all bursts. Currently this IP has a set well-known register map, which includes support for legacy and unroll modes. Legacy mode is version of this register map that has multiplexer register that allows to switch registers between all write and read channels and the unroll modes repeats all write and read channels registers with an offset between them. This register map is called v0. The IP team is creating a new register map more suitable to the latest PCIe features, that very likely will change the map register, which this version will be called v1. As soon as this new version is released by the IP team the support for this version in be included on this driver. According to the logic, patches 1, 2 and 3 should be squashed into 1 unique patch, but for the sake of simplicity of review, it was divided in this 3 patches files. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Russell King <rmk+kernel@armlinux.org.uk> Cc: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-06-04 15:29:22 +02:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dma: acpi-dma: introduce ACPI DMA helpers There is a new generic API to get a DMA channel for a slave device (commit 9a6cecc8 "dmaengine: add helper function to request a slave DMA channel"). In similar fashion to the DT case (commit aa3da644 "of: Add generic device tree DMA helpers") we introduce helpers to the DMAC drivers which are enumerated by ACPI. The proposed extension provides the following API calls: acpi_dma_controller_register(), devm_acpi_dma_controller_register() acpi_dma_controller_free(), devm_acpi_dma_controller_free() acpi_dma_simple_xlate() acpi_dma_request_slave_chan_by_index() acpi_dma_request_slave_chan_by_name() The first two should be used, for example, at probe() and remove() of the corresponding DMAC driver. At the register stage the DMAC driver supplies a custom xlate() function to translate a struct dma_spec into struct dma_chan. Accordingly to the ACPI Fixed DMA resource specification the only two pieces of information the slave device has are the channel id and the request line (slave id). Those two are represented by struct dma_spec. The acpi_dma_request_slave_chan_by_index() provides access to the specifix FixedDMA resource by its index. Whereas dma_request_slave_channel() takes a string parameter to identify the DMA resources required by the slave device. To make a slave device driver work with both DeviceTree and ACPI enumeration a simple convention is established: "tx" corresponds to the index 0 and "rx" to the index 1. In case of robust configuration the slave device driver unfortunately needs to call acpi_dma_request_slave_chan_by_index() directly. Additionally the patch provides "managed" version of the register/free pair i.e. devm_acpi_dma_controller_register() and devm_acpi_dma_controller_free(). Usually, the driver uses only devm_acpi_dma_controller_register(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-04-09 14:05:43 +03:00
dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 Add PDMA driver, sf-pdma, to enable DMA engine on HiFive Unleashed Rev A00 board. - Implement dmaengine APIs, support MEM_TO_MEM async copy. - Tested by DMA Test client - Supports 4 channels DMA, each channel has 1 done and 1 err interrupt connected to platform-level interrupt controller (PLIC). - Depends on DMA_ENGINE and DMA_VIRTUAL_CHANNELS The datasheet is here: https://static.dev.sifive.com/FU540-C000-v1.0.pdf Follow the DMAengine controller doc, "./Documentation/driver-api/dmaengine/provider.rst" to implement DMA engine. And use the dma test client in doc, "./Documentation/driver-api/dmaengine/dmatest.rst", to test. Each DMA channel has separate HW regs and support done and error ISRs. 4 channels share 1 done and 1 err ISRs. There's no expander/arbitrator in DMA HW. ------ ------ | |--< done 23 >--|ch 0| | |--< err 24 >--| | (dma0chan0) | | ------ | | ------ | |--< done 25 >--|ch 1| | |--< err 26 >--| | (dma0chan1) |PLIC| ------ | | ------ | |--< done 27 >--|ch 2| | |--< err 28 >--| | (dma0chan2) | | ------ | | ------ | |--< done 29 >--|ch 3| | |--< err 30 >--| | (dma0chan3) ------ ------ Signed-off-by: Green Wan <green.wan@sifive.com> Link: https://lore.kernel.org/r/20191107084955.7580-4-green.wan@sifive.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-11-07 16:49:21 +08:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
dmaengine: move drivers/of/dma.c -> drivers/dma/of-dma.c as requested by Rob Suggested-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-02-12 09:15:02 -08:00
dmaengine: ti: New directory for Texas Instruments DMA drivers Collect the Texas Instruments DMA drivers under drivers/dma/ti/ Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-04-25 11:45:03 +03:00
dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs DPPA2(Data Path Acceleration Architecture 2) qDMA supports virtualized channel by allowing DMA jobs to be enqueued into different work queues. Core can initiate a DMA transaction by preparing a frame descriptor(FD) for each DMA job and enqueuing this job through a hardware portal. DPAA2 components can also prepare a FD and enqueue a DMA job through a hardware portal. The qDMA prefetches DMA jobs through DPAA2 hardware portal. It then schedules and dispatches to internal DMA hardware engines, which generate read and write requests. Both qDMA source data and destination data can be either contiguous or non-contiguous using one or more scatter/gather tables. The qDMA supports global bandwidth flow control where all DMA transactions are stalled if the bandwidth threshold has been reached. Also supported are transaction based read throttling. Add NXP dppa2 qDMA to support some of Layerscape SoCs. such as: LS1088A, LS208xA, LX2, etc. Signed-off-by: Peng Ma <peng.ma@nxp.com> Link: https://lore.kernel.org/r/20190930020440.7754-2-peng.ma@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-09-30 02:04:40 +00:00
dmaengine: sort the Kconfig dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-24 13:43:14 +05:30
[I/OAT]: Setup the networking subsystem as a DMA client Attempts to allocate per-CPU DMA channels Signed-off-by: Chris Leech <christopher.leech@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-17 21:24:58 -07:00
I/OAT: Add DCA services Add code to connect to the DCA driver and provide cpu tags for use by drivers that would like to use Direct Cache Access hints. [Adrian Bunk] Several Kconfig cleanup items [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when built for uni-processor Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 01:27:42 -07:00
[I/OAT]: Setup the networking subsystem as a DMA client Attempts to allocate per-CPU DMA channels Signed-off-by: Chris Leech <christopher.leech@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-17 21:24:58 -07:00
dmaengine: allow dma support for async_tx to be toggled Provide a config option for blocking the allocation of dma channels to the async_tx api. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-03-25 09:13:25 -07:00
async_tx: remove HIGHMEM64G restriction This restriction prevented ASYNC_TX_DMA from being enabled on platform configurations where DMA address conversion could not be performed in place on the stack. Since commit 04ce9ab3 ("async_xor: permit callers to pass in a 'dma/page scribble' region") the async_tx api now either uses a caller provided 'scribble' buffer, or performs the conversion in place when sizeof(dma_addr_t) <= sizeof(struct page *). Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-09-08 15:06:10 -07:00
dmaengine: allow dma support for async_tx to be toggled Provide a config option for blocking the allocation of dma channels to the async_tx api. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-03-25 09:13:25 -07:00
dmatest: Simple DMA memcpy test client This client tests DMA memcpy using various lengths and various offsets into the source and destination buffers. It will initialize both buffers with a repeatable pattern and verify that the DMA engine copies the requested region and nothing more. It will also verify that the bytes aren't swapped around, and that the source buffer isn't modified. The dmatest module can be configured to test a specific device, a specific channel. It can also test multiple channels at the same time, and it can start multiple threads competing for the same channel. Changes since v2: * Support testing multiple channels at the same time * Support testing with multiple threads competing for the same channel * Use counting test patterns in order to catch byte ordering issues Changes since v1: * Remove extra dashes around "help" * Remove "default n" from Kconfig * Turn TEST_BUF_SIZE into a module parameter * Return DMA_NAK instead of DMA_DUP * Print unhandled events * Support testing specific channels and devices * Move to the end of the Makefile Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-08 11:58:45 -07:00
dmaengine: dmatest: Select DMA_ENGINE_RAID as its needed for the slave_sg test To enable usage of multiple SG buffers via the sg_buffers= module parameter, lets select DMA_ENGINE_RAID via Kconfig when DMATEST is configured. Otherwise the dmatest will "BUG" when more than 1 buffer (total of 2 for src + dst) is configured via sg_buffers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Kedareswara rao Appana <appanad@xilinx.com> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-04-27 14:21:40 +02:00
dmatest: Simple DMA memcpy test client This client tests DMA memcpy using various lengths and various offsets into the source and destination buffers. It will initialize both buffers with a repeatable pattern and verify that the DMA engine copies the requested region and nothing more. It will also verify that the bytes aren't swapped around, and that the source buffer isn't modified. The dmatest module can be configured to test a specific device, a specific channel. It can also test multiple channels at the same time, and it can start multiple threads competing for the same channel. Changes since v2: * Support testing multiple channels at the same time * Support testing with multiple threads competing for the same channel * Use counting test patterns in order to catch byte ordering issues Changes since v1: * Remove extra dashes around "help" * Remove "default n" from Kconfig * Turn TEST_BUF_SIZE into a module parameter * Return DMA_NAK instead of DMA_DUP * Print unhandled events * Support testing specific channels and devices * Move to the end of the Makefile Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-08 11:58:45 -07:00
dmaengine: fix enable for high order unmap pools The higher order mempools support raid operations, and we want to disable them when raid support is not enabled. Making them conditional on ASYNC_TX_DMA is not sufficient as other users (specifically dmatest) will also issue raid operations. Make raid drivers explicitly request that the core carry the higher order pools. Reported-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2013-12-09 10:33:16 -08:00
I/OAT: Add DCA services Add code to connect to the DCA driver and provide cpu tags for use by drivers that would like to use Direct Cache Access hints. [Adrian Bunk] Several Kconfig cleanup items [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when built for uni-processor Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 01:27:42 -07:00