2005-04-16 15:20:36 -07:00
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2021-10-13 15:36:22 +09:00
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2005-04-16 15:20:36 -07:00
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2016-03-31 10:05:33 +01:00
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2018-08-29 11:01:30 -07:00
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2019-10-01 21:53:44 +00:00
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2016-03-31 10:05:33 +01:00
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2016-12-14 15:09:43 +00:00
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2019-06-13 10:52:50 +02:00
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2008-02-26 21:54:54 +02:00
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2005-04-16 15:20:36 -07:00
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2007-10-22 19:10:57 +01:00
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2005-04-16 15:20:36 -07:00
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2007-10-22 19:10:57 +01:00
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2005-04-16 15:20:36 -07:00
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2005-09-03 15:56:16 -07:00
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2007-10-22 19:10:57 +01:00
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2005-04-16 15:20:36 -07:00
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2005-09-03 15:56:16 -07:00
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2007-10-22 19:10:57 +01:00
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2005-04-16 15:20:36 -07:00
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2021-05-02 02:24:36 +09:00
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2007-10-22 19:10:57 +01:00
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2007-11-12 17:30:52 +00:00
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2007-10-22 19:10:57 +01:00
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2005-04-16 15:20:36 -07:00
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MIPS: Tracing: Make function graph tracer work with -mmcount-ra-address
That thread "MIPS: Add option to pass return address location to
_mcount" from "David Daney <ddaney@caviumnetworks.com>" have added a new
option -mmcount-ra-address to gcc(4.5) for MIPS to transfer the location
of the return address to _mcount.
Benefit from this new feature, function graph tracer on MIPS will be
easier and safer to hijack the return address of the kernel function,
which will save some overhead and make the whole thing more reliable.
In this patch, at first, try to enable the option -mmcount-ra-address in
arch/mips/Makefile with cc-option, if gcc support it, it will be
enabled, otherwise, no side effect.
and then, we need to support this new option of gcc 4.5 and also support
the old gcc versions.
with _mcount in the old gcc versions, it's not easy to get the location
of return address(tracing: add function graph tracer support for MIPS),
so, we do it in a C function: ftrace_get_parent_addr(ftrace.c), but
with -mmcount-ra-address, only several instructions need to get what
we want, so, I put into asm(mcount.S). and also, as the $12(t0) is
used by -mmcount-ra-address for transferring the localtion of return
address to _mcount, we need to save it into the stack and restore it
when enabled dynamic function tracer, 'Cause we have called
"ftrace_call" before "ftrace_graph_caller", which may destroy
$12(t0).
(Thanks to David for providing that -mcount-ra-address and giving the
idea of KBUILD_MCOUNT_RA_ADDRESS, both of them have made the whole
thing more beautiful!)
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Nicholas Mc Guire <der.herr@hofr.at>
Cc: zhangfx@lemote.com
Cc: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/681/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-20 20:34:38 +08:00
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2009-04-28 19:28:33 +02:00
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2009-04-28 19:38:35 +02:00
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2006-02-22 23:06:55 +00:00
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2005-04-16 15:20:36 -07:00
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2006-03-08 11:35:00 +00:00
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2006-02-22 23:06:55 +00:00
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2005-04-16 15:20:36 -07:00
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2006-02-22 23:06:55 +00:00
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2006-03-08 11:35:00 +00:00
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2007-07-28 13:27:21 +01:00
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2009-10-14 18:12:16 +08:00
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2005-04-16 15:20:36 -07:00
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2023-01-11 20:04:59 -07:00
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2005-02-21 11:22:15 +00:00
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kbuild: allow assignment to {A,C,LD}FLAGS_MODULE on the command line
It is now possible to assign options to AS, CC and LD
on the command line - which is only used when building modules.
{A,C,LD}FLAGS_MODULE was all used both in the top-level Makefile
in the arch makefiles, thus users had no way to specify
additional options to AS, CC, LD when building modules
without overriding the original value.
Introduce a new set of variables KBUILD_{A,C,LD}FLAGS_MODULE
that is used by arch specific files and free up
{A,C,LD}FLAGS_MODULE so they can be assigned on
the command line.
All arch Makefiles that used the old variables has been updated.
Note: Previously we had a MODFLAGS variable for both
AS and CC. But in favour of consistency this was dropped.
So in some cases arch Makefile has one assignmnet replaced by
two assignmnets.
Note2: MODFLAGS was not documented and is dropped
without any notice. I do not expect much/any breakage
from this.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Cc: Denys Vlasenko <vda.linux@googlemail.com>
Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Chen Liqin <liqin.chen@sunplusct.com>
Acked-by: Mike Frysinger <vapier@gentoo.org> [blackfin]
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> [avr32]
Signed-off-by: Michal Marek <mmarek@suse.cz>
2010-07-28 17:33:09 +02:00
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2005-04-16 15:20:36 -07:00
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2006-06-07 13:25:37 +01:00
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2018-08-07 16:06:41 -07:00
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2005-07-07 09:19:31 +00:00
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2006-03-18 16:59:31 +00:00
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2017-01-28 22:24:16 -05:00
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2021-01-09 20:30:47 +01:00
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2023-01-11 20:05:00 -07:00
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2021-01-09 20:30:47 +01:00
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2005-04-16 15:20:36 -07:00
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2024-02-02 18:21:42 +00:00
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2018-06-18 17:37:59 -07:00
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mips: Add MIPS Release 5 support
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21 17:07:14 +03:00
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MIPS: build: Fix "-modd-spreg" switch usage when compiling for mips32r6
Add "-modd-spreg" when compiling the kernel for mips32r6 target.
This makes sure the kernel builds properly even with toolchains that
use "-mno-odd-spreg" by default. This is the case with Android gcc.
Prior to this patch, kernel builds using gcc for Android failed with
following error messages, if target architecture is set to mips32r6:
arch/mips/kernel/r4k_switch.S: Assembler messages:
.../r4k_switch.S:210: Error: float register should be even, was 1
.../r4k_switch.S:212: Error: float register should be even, was 3
.../r4k_switch.S:214: Error: float register should be even, was 5
.../r4k_switch.S:216: Error: float register should be even, was 7
.../r4k_switch.S:218: Error: float register should be even, was 9
.../r4k_switch.S:220: Error: float register should be even, was 11
.../r4k_switch.S:222: Error: float register should be even, was 13
.../r4k_switch.S:224: Error: float register should be even, was 15
.../r4k_switch.S:226: Error: float register should be even, was 17
.../r4k_switch.S:228: Error: float register should be even, was 19
.../r4k_switch.S:230: Error: float register should be even, was 21
.../r4k_switch.S:232: Error: float register should be even, was 23
.../r4k_switch.S:234: Error: float register should be even, was 25
.../r4k_switch.S:236: Error: float register should be even, was 27
.../r4k_switch.S:238: Error: float register should be even, was 29
.../r4k_switch.S:240: Error: float register should be even, was 31
make[2]: *** [arch/mips/kernel/r4k_switch.o] Error 1
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Cc: James.Hogan@imgtec.com
Cc: Paul.Burton@imgtec.com
Cc: Raghu.Gandham@imgtec.com
Cc: Leonid.Yegoshin@imgtec.com
Cc: Douglas.Leung@imgtec.com
Cc: Petar.Jovanovic@imgtec.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-06-19 17:50:09 +02:00
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2018-06-18 17:37:59 -07:00
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|
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|
mips: Add MIPS Release 5 support
There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.
Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.
So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.
So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.
Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-05-21 17:07:14 +03:00
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2014-10-27 10:34:11 +00:00
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2024-02-02 18:21:42 +00:00
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2008-10-24 01:27:57 +09:00
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2024-02-02 18:21:42 +00:00
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2005-04-16 15:20:36 -07:00
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2024-02-02 18:21:42 +00:00
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2005-04-16 15:20:36 -07:00
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2024-02-02 18:21:42 +00:00
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2024-07-14 10:52:57 +08:00
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2005-04-16 15:20:36 -07:00
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2014-06-29 00:59:35 +01:00
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2024-02-02 18:21:42 +00:00
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2005-04-16 15:20:36 -07:00
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2024-02-02 18:21:41 +00:00
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2010-10-07 16:03:53 -07:00
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2024-02-02 18:21:43 +00:00
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2005-04-16 15:20:36 -07:00
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2024-02-02 18:21:42 +00:00
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2023-04-04 10:33:47 +01:00
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2024-02-02 18:21:44 +00:00
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2023-04-04 10:33:47 +01:00
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2007-10-23 12:43:11 +01:00
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2023-04-04 10:33:47 +01:00
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2007-10-23 12:43:11 +01:00
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2015-02-02 15:41:01 +00:00
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2015-04-02 14:42:52 +01:00
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2015-02-02 15:41:01 +00:00
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2015-04-02 14:42:52 +01:00
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2015-02-02 15:41:01 +00:00
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2016-05-16 12:50:04 +01:00
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2017-11-22 11:30:30 +00:00
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2018-02-09 22:11:06 +00:00
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2018-10-15 18:26:12 +00:00
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2019-02-02 01:43:27 +00:00
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2015-02-02 15:41:01 +00:00
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2005-04-16 15:20:36 -07:00
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2012-11-15 20:48:50 +01:00
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2008-01-04 23:31:07 +01:00
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2005-04-16 15:20:36 -07:00
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2010-02-26 13:57:12 +01:00
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2018-01-15 22:29:54 -05:00
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2010-02-26 13:57:12 +01:00
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2005-04-16 15:20:36 -07:00
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2021-07-25 03:35:56 +09:00
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2009-06-24 11:12:57 +02:00
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2012-10-25 16:23:31 +02:00
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2013-01-22 12:59:30 +01:00
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2012-10-25 16:23:31 +02:00
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2017-08-07 16:16:47 -07:00
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2018-08-29 11:01:30 -07:00
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2008-09-16 19:48:51 +02:00
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2005-04-16 15:20:36 -07:00
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2007-02-15 12:06:48 +01:00
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2007-02-15 14:21:36 +01:00
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2007-02-15 12:06:48 +01:00
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2007-02-15 14:21:36 +01:00
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2007-02-15 12:06:48 +01:00
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2024-02-02 18:21:40 +00:00
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2007-02-15 12:06:48 +01:00
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2023-07-18 15:37:18 +01:00
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2007-10-23 12:43:11 +01:00
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2007-09-27 16:26:40 +02:00
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2007-02-15 12:06:48 +01:00
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2020-05-06 13:52:45 +08:00
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2007-10-15 21:59:31 +02:00
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2009-09-20 12:28:22 +02:00
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|
2020-05-06 13:52:45 +08:00
|
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|
2012-05-10 14:22:10 +02:00
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|
2005-04-16 15:20:36 -07:00
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2013-08-30 16:42:41 +01:00
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|
2020-05-06 13:52:45 +08:00
|
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|
2016-10-05 18:18:19 +01:00
|
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|
2017-08-07 15:37:21 -07:00
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2016-10-05 18:18:20 +01:00
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2013-08-30 16:42:41 +01:00
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2017-08-10 13:27:39 -05:00
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2018-08-24 08:20:39 +09:00
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|
2005-04-16 15:20:36 -07:00
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|
2023-07-18 15:37:23 +01:00
|
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|
2023-06-01 11:38:24 -07:00
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|
2022-11-18 16:28:11 +08:00
|
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|
2015-05-11 23:37:05 +03:00
|
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|
2006-03-08 11:35:00 +00:00
|
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|
2005-04-16 15:20:36 -07:00
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2018-11-07 23:14:10 +00:00
|
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|
2005-04-16 15:20:36 -07:00
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|
2009-06-04 20:27:10 +08:00
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2013-08-30 16:42:40 +01:00
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2013-08-30 16:42:42 +01:00
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2015-02-16 15:13:11 +00:00
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|
2013-08-30 16:42:42 +01:00
|
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2015-02-16 15:13:11 +00:00
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2016-10-05 18:18:19 +01:00
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2013-08-30 16:42:40 +01:00
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2016-10-31 15:19:55 +01:00
|
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|
2020-11-01 15:13:01 +00:00
|
|
|
|
2013-08-30 16:42:40 +01:00
|
|
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|
2005-04-16 15:20:36 -07:00
|
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|
2010-11-10 00:26:34 +08:00
|
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|
|
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|
2005-04-16 15:20:36 -07:00
|
|
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|
2010-11-10 00:26:34 +08:00
|
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|
2005-04-16 15:20:36 -07:00
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2010-11-10 00:26:34 +08:00
|
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|
2005-04-16 15:20:36 -07:00
|
|
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|
2010-11-10 00:26:34 +08:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2019-06-13 10:52:50 +02:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2010-05-30 16:28:03 +02:00
|
|
|
|
2013-08-30 16:42:40 +01:00
|
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|
2013-08-30 16:42:41 +01:00
|
|
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|
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|
2005-04-16 15:20:36 -07:00
|
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|
2013-09-11 11:34:48 +01:00
|
|
|
|
2010-05-30 16:28:03 +02:00
|
|
|
|
2013-08-30 16:42:40 +01:00
|
|
|
|
2010-05-30 16:28:03 +02:00
|
|
|
|
2020-11-01 15:12:52 +00:00
|
|
|
|
2013-09-11 11:34:48 +01:00
|
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2010-05-30 16:28:03 +02:00
|
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|
|
2010-05-30 16:28:31 +02:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2007-05-30 00:38:07 +09:00
|
|
|
|
|
|
|
|
|
2026-04-02 16:36:20 +02:00
|
|
|
|
2007-05-30 00:38:07 +09:00
|
|
|
|
|
|
|
|
|
2026-04-02 16:36:20 +02:00
|
|
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|
2007-05-30 00:38:07 +09:00
|
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|
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|
|
|
2009-03-30 14:49:40 +02:00
|
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|
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|
|
2011-06-21 17:58:55 +01:00
|
|
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|
2009-10-14 18:12:16 +08:00
|
|
|
|
2011-06-21 17:58:55 +01:00
|
|
|
|
2009-03-30 14:49:40 +02:00
|
|
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|
|
2018-12-13 14:37:39 +05:30
|
|
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|
|
|
2007-07-28 13:38:49 +01:00
|
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|
2009-03-30 14:49:40 +02:00
|
|
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|
2007-07-28 13:38:49 +01:00
|
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|
2014-10-07 21:33:04 -04:00
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|
2009-10-14 18:12:16 +08:00
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|
2013-08-30 16:42:42 +01:00
|
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|
2015-02-16 15:13:11 +00:00
|
|
|
|
|
|
|
|
|
2013-08-30 16:42:42 +01:00
|
|
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|
2015-02-16 15:13:11 +00:00
|
|
|
|
|
|
|
|
|
2016-10-31 15:19:55 +01:00
|
|
|
|
2007-07-28 13:38:49 +01:00
|
|
|
|
2011-03-30 22:57:33 -03:00
|
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|
2016-10-05 18:18:20 +01:00
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2018-02-09 16:11:58 +00:00
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|
2016-10-05 18:18:20 +01:00
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|
2007-07-28 13:38:49 +01:00
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|
2016-10-05 18:18:20 +01:00
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2018-02-09 16:11:58 +00:00
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2016-10-05 18:18:20 +01:00
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2017-08-07 16:01:12 -07:00
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2017-03-13 15:57:14 +01:00
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|
2016-10-05 18:18:20 +01:00
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2016-10-05 18:18:21 +01:00
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2017-08-07 16:01:15 -07:00
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2016-10-05 18:18:21 +01:00
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2018-03-20 14:08:00 +01:00
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2018-02-09 16:11:56 +00:00
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2016-10-05 18:18:21 +01:00
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2018-02-09 16:11:56 +00:00
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2017-03-31 10:00:42 +01:00
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|
2018-02-09 16:11:56 +00:00
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2021-07-23 10:25:43 +08:00
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2018-02-09 16:11:56 +00:00
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