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License cleanup: add SPDX GPL-2.0 license identifier to files with no license Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 15:07:57 +01:00
ARM: u300: convert to common clock This converts the U300 clock implementation over to use the common struct clk and moves the implementation down into drivers/clk. Since VCO isn't used in tree it was removed, it's not hard to put it back in if need be. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [mturquette@linaro.org: trivial Makefile conflict] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-06-19 23:44:25 +02:00
clkdev: remove CONFIG_CLKDEV_LOOKUP This option is now synonymous with CONFIG_HAVE_CLK, so use the latter globally. Any out-of-tree platform ports that still use a private clk_get()/clk_put() implementation should move to CONFIG_COMMON_CLK. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-05-31 11:48:49 +02:00
clk: beautify Makefile The list of common clock types was getting a bit unmanageable. This patch puts only one file on each line and reorders the object files alphabetically. Also a newline is added to separate the sections. Reported-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-01-18 13:00:05 -08:00
clk: Add KUnit tests for clks registered with struct clk_parent_data Test that clks registered with 'struct clk_parent_data' work as intended and can find their parents. Cc: Christian Marangi <ansuelsmth@gmail.com> Cc: Brendan Higgins <brendan.higgins@linux.dev> Reviewed-by: David Gow <davidgow@google.com> Cc: Rae Moar <rmoar@google.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240718210513.3801024-9-sboyd@kernel.org
2024-07-18 14:05:07 -07:00
clk: test: Add KUnit tests for clock-assigned-rates{-u64} DT properties Add unit tests for the two types of assigned rate properties. Test different combinations of assigned clocks and make sure that rates aren't assigned when the DT properties are malformed or are zero. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240822002433.1163814-4-sboyd@kernel.org
2024-08-21 17:24:30 -07:00
clk: Add KUnit tests for assigned-clock-sscs Add KUnit test coverage for the assigned-clock-sscs DT property that configures spread spectrum on clocks before they are used. Extend the existing test infrastructure to support spread spectrum: - Add struct clk_spread_spectrum field to clk_dummy_context and a clk_dummy_set_spread_spectrum callback - Wire set_spread_spectrum into all dummy clock ops - Extend clk_assigned_rates_register_clk and test parameter struct to propagate initial SSCS values Add a new separate test suite clk_assigned_sscs with three categories: 1. clk_assigned_sscs_assigns_one — verifies that a single assigned-clock-sscs entry correctly configures spread spectrum on one clock, testing both provider and consumer paths 2. clk_assigned_sscs_assigns_multiple — verifies that multiple assigned-clock-sscs entries configure spread spectrum on two clocks, testing both provider and consumer paths 3. clk_assigned_sscs_skips — verifies that malformed DT properties are correctly skipped without error: missing assigned-clocks, zero-valued SSCS, and null phandles, tested for both provider and consumer scenarios New DT overlays are added for all test scenarios: - kunit_clk_assigned_sscs_one{,consumer} — single valid entry - kunit_clk_assigned_sscs_multiple{,consumer} — two valid entries - kunit_clk_assigned_sscs_without{,consumer} — missing assigned-clocks - kunit_clk_assigned_sscs_zero{,consumer} — all-zero SSCS values - kunit_clk_assigned_sscs_null{,consumer} — null phandle Co-developed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-06-12 16:46:26 +08:00
clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests Add kunit test suites clk_hw_get_dev() and clk_hw_get_of_node() for clocks registered with clk_hw_register() and of_clk_hw_register() Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20250417-clk-hw-get-helpers-v1-2-7743e509612a@baylibre.com Reviewed-by: Brian Masney <bmasney@redhat.com> [sboyd@kernel.org: Drop genparams, rename tests, drop inits, combine suites, add test for non-DT platform device] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-04-17 15:44:23 +02:00
clk: Add KUnit tests for clks registered with struct clk_parent_data Test that clks registered with 'struct clk_parent_data' work as intended and can find their parents. Cc: Christian Marangi <ansuelsmth@gmail.com> Cc: Brendan Higgins <brendan.higgins@linux.dev> Reviewed-by: David Gow <davidgow@google.com> Cc: Rae Moar <rmoar@google.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240718210513.3801024-9-sboyd@kernel.org
2024-07-18 14:05:07 -07:00
clk: beautify Makefile The list of common clock types was getting a bit unmanageable. This patch puts only one file on each line and reorders the object files alphabetically. Also a newline is added to separate the sections. Reported-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-01-18 13:00:05 -08:00
clk: divider: Add KUnit tests for clk_divider_bestdiv() ULONG_MAX handling Add KUnit tests to verify the behaviour of clk_divider_bestdiv() when clk_round_rate() is called with ULONG_MAX, which is the canonical way to probe the maximum rate a clock can produce. Two test cases are introduced: - clk_divider_bestdiv_ulong_max_returns_max_rate: registers a 1 GHz fixed-rate parent driving a table-based divider whose smallest entry is div=2 (entries: 2, 4, 8). Calls clk_hw_round_rate(div_hw, ULONG_MAX) and checks the result. - clk_divider_bestdiv_mux_ulong_max_returns_max_rate: places a two-input mux (4 GHz and 2 GHz fixed-rate parents, CLK_SET_RATE_PARENT) ahead of the same table-based divider to verify correct parent selection under ULONG_MAX. Both tests use an explicit clk_div_table with a minimum divider of 2 so that the pre-loop maxdiv clamping in clk_divider_bestdiv(): maxdiv = min(ULONG_MAX / rate, maxdiv); clamps maxdiv to 1, causing _next_div() to return 2 on the first iteration and skip the loop body entirely. This makes bestdiv fall back to the maximum divider, returning the minimum rate rather than the maximum. The expected values intentionally reflect the buggy output: - test 1: PARENT_RATE_1GHZ / 8 (minimum rate, not maximum) - test 2: 0 (invalid, loop never populated bestdiv) These will be corrected to PARENT_RATE_1GHZ / 2 and PARENT_RATE_4GHZ / 2 respectively once the fix to clk_divider_bestdiv() is applied. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-06-02 21:02:42 +01:00
clk: beautify Makefile The list of common clock types was getting a bit unmanageable. This patch puts only one file on each line and reorders the object files alphabetically. Also a newline is added to separate the sections. Reported-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-01-18 13:00:05 -08:00
clk: Add KUnit tests for clk fixed rate basic type Test that the fixed rate basic type clk works as intended. Cc: Brendan Higgins <brendan.higgins@linux.dev> Cc: David Gow <davidgow@google.com> Cc: Rae Moar <rmoar@google.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240718210513.3801024-8-sboyd@kernel.org
2024-07-18 14:05:06 -07:00
clk: beautify Makefile The list of common clock types was getting a bit unmanageable. This patch puts only one file on each line and reorders the object files alphabetically. Also a newline is added to separate the sections. Reported-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-01-18 13:00:05 -08:00
clk: gate: Add some kunit test suites Test various parts of the clk gate implementation with the kunit testing framework. Reviewed-by: Brendan Higgins <brendanhiggins@google.com> Acked-by: Daniel Latypov <dlatypov@google.com> Cc: <kunit-dev@googlegroups.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220120175902.2165958-1-sboyd@kernel.org
2022-01-20 09:59:02 -08:00
clk: Add a basic multiplier clock Some clocks are using a multiplier component, however, unlike their mux, gate or divider counterpart, these factors don't have a basic clock implementation. This leads to code duplication across platforms that want to use that kind of clocks, and the impossibility to use the composite clocks with such a clock without defining your own rate operations. Create such a driver in order to remove these issues, and hopefully factor the implementations, reducing code size across platforms and consolidating the various implementations. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2015-05-19 22:19:33 +02:00
clk: beautify Makefile The list of common clock types was getting a bit unmanageable. This patch puts only one file on each line and reorders the object files alphabetically. Also a newline is added to separate the sections. Reported-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-01-18 13:00:05 -08:00
clk: Add composite clock type Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-20 17:30:34 +05:30
clk: new basic clk type for fractional divider Fractional divider clocks are fairly common. This adds basic type for them. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2014-05-15 16:40:25 +03:00
clk: fractional-divider: tests: Add test suite for edge cases In light of the recent discovery that the fractional divisor approximation does not utilize the full available range for clocks that are flagged CLK_FRAC_DIVIDER_ZERO_BASED [1], implement tests for the edge cases of this clock type. Signed-off-by: Frank Oltmanns <frank@oltmanns.dev> Link: https://lore.kernel.org/lkml/20230529133433.56215-1-frank@oltmanns.dev [1] Link: https://lore.kernel.org/r/20230617131041.18313-3-frank@oltmanns.dev [sboyd@kernel.org: Rename suite and tests slightly, drop unused includes, store parent rate to compare instead of repeating equation] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-06-17 15:10:41 +02:00
clk: Rename clk-gpio-gate.c to clk-gpio.c The file clk-gpio-gate.c does not only contain the gate clock, but also the mux clock. Rename the file to clk-gpio.c. Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by: Sergej Sawazki <ce3a@gmx.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-28 16:24:56 +02:00
clk: Support for clock parents and rates assigned from device tree This patch adds helper functions to configure clock parents and rates as specified through 'assigned-clock-parents', 'assigned-clock-rates' DT properties for a clock provider or clock consumer device. The helpers are now being called by the bus code for the platform, I2C and SPI busses, before the driver probing and also in the clock core after registration of a clock provider. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-06-18 17:29:32 +02:00
clk: beautify Makefile The list of common clock types was getting a bit unmanageable. This patch puts only one file on each line and reorders the object files alphabetically. Also a newline is added to separate the sections. Reported-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-01-18 13:00:05 -08:00
clk: Add test managed clk provider/consumer APIs Unit tests are more ergonomic and simpler to understand if they don't have to hoist a bunch of code into the test harness init and exit functions. Add some test managed wrappers for the clk APIs so that clk unit tests can write more code in the actual test and less code in the harness. Only add APIs that are used for now. More wrappers can be added in the future as necessary. Cc: Brendan Higgins <brendan.higgins@linux.dev> Cc: David Gow <davidgow@google.com> Cc: Rae Moar <rmoar@google.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240718210513.3801024-7-sboyd@kernel.org
2024-07-18 14:05:05 -07:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: Makefile: re-sort and clean up Sorting is hard. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-15 17:09:25 -07:00
clk: clk-apple-nco: Add driver for Apple NCO Add a common clock driver for NCO blocks found on Apple SoCs where they are typically the generators of audio clocks. Signed-off-by: Martin Povišer <povik+lin@cutebit.org> Link: https://lore.kernel.org/r/20220208183411.61090-3-povik+lin@cutebit.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-02-08 19:34:10 +01:00
ARM: clk: add clk-asm9260 driver Provide CLK support for Alphascale ASM9260 SoC. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-20 10:23:02 +01:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: Add clock driver for AXM55xx SoC Add clk driver to support clock blocks found on the AXM55xx devices. The driver provides clock implementations for three different types of clock devices on the AXM55xx device: PLL clock, a clock divider and a clock mux. Signed-off-by: Anders Berg <anders.berg@lsi.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-15 15:42:25 +02:00
clk: bd718x7: Initial support for ROHM bd71837/bd71847 PMIC clock ROHM bd71837 and bd71847 contain 32768Hz clock gate. Support the clock using generic clock framework. Note, only bd71837 is tested but bd71847 should be identical what comes to clk parts. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-07 12:01:44 +02:00
clk: Add common clock driver for BM1880 SoC Add common clock driver for Bitmain BM1880 SoC. The clock controller on BM1880 has supplies clocks to all peripherals in the form of gate clocks and composite clocks (fixed factor + gate). Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lkml.kernel.org/r/20191115162901.17456-7-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-11-15 21:59:00 +05:30
clk: TI CDCE706 clock synthesizer driver The driver allows using CDCE706 in its default configuration recorded in EEPROM and adjusting of synthesized clocks by consumers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-12 10:20:46 +03:00
clk: Makefile: re-sort and clean up Sorting is hard. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-15 17:09:25 -07:00
clk: Add CLPS711X clk driver This adds the clock driver for Cirrus Logic CLPS711X series SoCs using common clock infrastructure. Designed primarily for migration CLPS711X subarch for multiplatform & DT, for this as the "OF" and "non-OF" calls implemented. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-13 08:37:52 +04:00
clk: Makefile: re-sort and clean up Sorting is hard. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-15 17:09:25 -07:00
clk: ep93xx: add DT support for Cirrus EP93xx Rewrite EP93xx clock driver located in arch/arm/mach-ep93xx/clock.c trying to do everything the device tree way: - provide clock acces via of - drop clk_hw_register_clkdev - drop init code and use module_auxiliary_driver Co-developed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-09 11:10:28 +03:00
clk: sparx5: Add Sparx5 SoC DPLL clock driver This adds a device driver for the Sparx5 SoC DPLL clock Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200727084211.6632-9-lars.povlsen@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-27 10:42:09 +02:00
clk: en7523: Add clock driver for Airoha EN7523 SoC This driver only registers fixed rate clocks, since the clocks are fully initialized by the boot loader and should not be changed later, according to Airoha. Signed-off-by: Felix Fietkau <nbd@nbd.name> Link: https://lore.kernel.org/r/20220314084409.84394-3-nbd@nbd.name Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-14 09:44:04 +01:00
clk: eyeq: add driver Add Mobileye EyeQ5, EyeQ6L and EyeQ6H clock controller driver. It is both a platform driver and a hook onto of_clk_init() used for clocks required early (GIC timer, UARTs). For some compatible, it is both at the same time. eqc_early_init() initialises early PLLs and exposes its own clock provider. It marks other clocks as deferred. eqc_probe() adds all remaining clocks using another clock provider. It exposes read-only PLLs derived from the main crystal on board. It also exposes another type of clocks: divider clocks. They always have even divisors and have one PLL as parent. This driver also bears the responsability for optional reset and pinctrl auxiliary devices. The match data attached to the devicetree node compatible indicate if such devices should be created. They all get passed a pointer to the start of the OLB region. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://lore.kernel.org/r/20241023-mbly-clk-v6-1-ca83e43daf93@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-10-23 12:58:40 +02:00
clk: Add Fixed MMIO clock driver This patch adds a driver for Fixed MMIO clock. The driver reads a clock frequency value from a single 32-bit memory mapped register and registers it as a fixed rate clock. It can be enabled with COMMON_CLK_FIXED_MMIO Kconfig option. Signed-off-by: Jan Kotas <jank@cadence.com> [sboyd@kernel.org: Make of_fixed_mmio_clk_setup() static, use clk_hw based APIs] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-13 12:49:29 +00:00
clk: fsl-flexspi: new driver Add support for the FlexSPI clock on Freescale Layerscape SoCs. The clock is a simple divider based one and is located inside the device configuration space (DCFG). This will allow switching the SCK frequencies for the FlexSPI interface on the LS1028A and the LX2160A. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20201108185113.31377-8-michael@walle.cc [sboyd@kernel.org: Drop modalias, add module table] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-08 19:51:11 +01:00
clk: fsl-sai: new driver With this driver it is possible to use the BCLK pin of the SAI module as a generic clock output. This is esp. useful if you want to drive a clock to an audio codec. Because the output only allows integer divider values the audio codec needs an integrated PLL. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lkml.kernel.org/r/20200102231101.11834-3-michael@walle.cc Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-03 00:11:01 +01:00
clk: Add Gemini SoC clock controller The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock controller that derive all clocks from a single crystal, using some documented and some undocumented PLLs, half dividers, counters and gates. This is a best attempt to construct a clock driver for the clocks so at least we can gate off unused hardware and driver the PCI bus clock. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [sboyd@codeaurora.org: Fix devm_ioremap_resource() return value checking] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21 09:59:52 +02:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
ARC: clk: introduce HSDK pll driver HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi. By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-25 20:39:14 +03:00
clk: Add RISC-V Canaan Kendryte K210 clock driver Add a clock provider driver for the Canaan Kendryte K210 RISC-V SoC. This new driver with the compatible string "canaan,k210-clk" implements support for the full clock structure of the K210 SoC. Since it is required for the correct operation of the SoC, this driver is selected by default for compilation when the SOC_CANAAN option is selected. With this change, the k210-sysctl driver is turned into a simple platform driver which enables its power bus clock and triggers populating its child nodes. The sysctl driver retains the SOC early initialization code, but the implementation now relies on the new function k210_clk_early_init() provided by the new clk-k210 driver. The clock structure implemented and many of the coding ideas for the driver come from the work by Sean Anderson on the K210 support for the U-Boot project. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-02-10 14:02:14 +09:00
clk: canaan: Add clock driver for Canaan K230 This patch provides basic support for the K230 clock, which covers all clocks in K230 SoC. The clock tree of the K230 SoC consists of a 24MHZ external crystal oscillator, PLLs and an external pulse input for timerX, and their derived clocks. Co-developed-by: Troy Mitchell <TroyMitchell988@gmail.com> Signed-off-by: Troy Mitchell <TroyMitchell988@gmail.com> Signed-off-by: Xukai Wang <kingxukai@zohomail.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-04-25 17:29:32 +08:00
clk: add support for the lmk04832 The LMK04832 is an ultra-high performance clock conditioner with JEDEC JESD204B support and is also pin compatible with the LMK0482x family of devices. Signed-off-by: Liam Beguin <lvb@xiphos.com> Link: https://lore.kernel.org/r/20210423004057.283926-2-liambeguin@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-04-22 20:40:55 -04:00
clk: lan966x: Add lan966x SoC clock driver This adds Generic Clock Controller driver for lan966x SoC. Lan966x clock controller contains 3 PLLs - cpu_clk, ddr_clk and sys_clk. It generates and supplies clock to various peripherals within SoC. Register settings required to provide GCK clocking to a peripheral is as below: GCK_SRC_SEL = Select clock source. GCK_PRESCALER = Set divider value. GCK_ENA = 1 - Enable GCK clock. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Co-developed-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211103061935.25677-4-kavyasree.kotagiri@microchip.com
2021-11-03 11:49:35 +05:30
clk: lochnagar: Add support for the Cirrus Logic Lochnagar Lochnagar is an evaluation and development board for Cirrus Logic Smart CODEC and Amp devices. It allows the connection of most Cirrus Logic devices on mini-cards, as well as allowing connection of various application processor systems to provide a full evaluation platform. This driver supports the board controller chip on the Lochnagar board. The Lochnagar can take several input clocks from the host system, provides several of its own clock sources, and provides extensive routing options for those clocks to be supplied to the attached CODEC/Amp device. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-03-19 13:37:00 +00:00
clk: loongson1: Re-implement the clock driver Re-implement the clock driver for Loongson-1 to add devicetree support and fit into the clock framework. Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com> Link: https://lore.kernel.org/r/20230321111817.71756-4-keguang.zhang@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-21 19:18:16 +08:00
clk: clk-loongson2: add clock controller driver support This driver provides support for clock controller on Loongson-2 SoC, the Loongson-2 SoC uses a 100MHz clock as the PLL reference clock, there are five independent PLLs inside, each of which PLL can provide up to three sets of frequency dependent clock outputs. Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> Link: https://lore.kernel.org/r/20230323025229.2971-2-zhuyinbo@loongson.cn Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-03-23 10:52:29 +08:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: Add driver for MAX9485 This patch adds a driver for MAX9485, a programmable audio clock generator. The device requires a 27.000 MHz clock input. It can provide a gated buffered output of its input clock and two gated outputs of a PLL that can generate one out of 16 discrete frequencies. There is only one PLL however, so the two gated outputs will always have the same frequency but they can be switched individually. The driver for this device exposes 4 clocks in total: - MAX9485_MCLKOUT: A gated, buffered output of the input clock - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete frequencies - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT Some PLL output frequencies can be achieved with different register settings. The driver will select the one with lowest jitter in such cases. Signed-off-by: Daniel Mack <daniel@zonque.org> [sboyd@kernel.org: Use local variable for val in max9485_clkout_recalc_rate() and shorten line of max9485_of_clk_get()] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06 20:53:03 +02:00
clock: milbeaut: Add Milbeaut M10V clock controller The M10V of the Milbeaut SoCs has an on-chip controller that derive mostly clocks from a single external clock, using PLLs, dividers, multiplexers and gates. Since the PLLs have already been started and will not stop / restart, they are fixed factor. The gates will be added in later patch (all of the gates are off state now). Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-25 19:41:01 +09:00
clk: add MOXA ART SoCs clock driver MOXA ART SoCs allow to determine PLL output and APB frequencies by reading registers holding multiplier and divisor information. Add a clock driver for this SoC. Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-28 12:09:11 +01:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: npcm7xx: add clock controller Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which generates and supplies clocks to all modules within the BMC. Signed-off-by: Tali Perry <tali.perry1@gmail.com> [sboyd@kernel.org: Drop clk_get()s, cleanup whitespace, drop unused includes, fix static checker warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-26 13:16:26 +03:00
clk: npcm8xx: add clock controller Add auxiliary driver to support Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller which generates and supplies clocks to all modules within the BMC. The NPCM8xx clock controller is created using the auxiliary device framework and set up in the npcm reset driver since the NPCM8xx clock is using the same register region. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Benjamin Fair <benjaminfair@google.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20240912191038.981105-4-tmaimon77@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-09-12 22:10:38 +03:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: Add driver for Palmas clk32kg and clk32kgaudio clocks Palmas class of devices can provide 32K clock(s) to be used by other devices on the board. Depending on the actual device the provided clocks can be: CLK32K_KG and CLK32K_KGAUDIO or only one: CLK32K_KG (TPS659039 for example) Use separate compatible flags for the two 32K clock. A system which needs or have only one of the 32k clock from Palmas will need to add node(s) for each clock as separate section in the dts file. The two compatible property is: "ti,palmas-clk32kg" for clk32kg clock "ti,palmas-clk32kgaudio" for clk32kgaudio clock Apart from the register control of the clocks - which is done via the clock API there is a posibility to enable the external sleep control. In this way the clock can be enabled/disabled on demand by the user of the clock. See the documentation for more details. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-06-27 09:01:11 +03:00
clk: ls1028a: Add clock driver for Display output interface Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY), as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable integer division and range of the display output pixel clock's 27-594MHz. Signed-off-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lkml.kernel.org/r/20191213083402.35678-2-wen.he_1@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-13 16:34:02 +08:00
clk: Makefile: re-sort and clean up Sorting is hard. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-15 17:09:25 -07:00
clk: ppc-corenet: rename driver to clk-qoriq Freescale introduced new ARM-based socs which using the compatible clock IP block with PowerPC-based socs'. So this driver can be used on both platforms. Updated relevant descriptions and renamed this driver to better represent its meaning and keep the function of driver untouched. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-15 14:03:41 +08:00
clk: RK808: add clkout driver for RK808 This is the initial version of the RK808 PMIC. This is a power management IC for multimedia products. It provides regulators that are able to supply power to processor cores and other components. The chip provides other modules including RTC, Clockout. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Samuel Ortiz <sameo@linux.intel.com> says: Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Olof Johansson <olof@lixom.net> Cc: Dmitry Torokhov <dtor@chromium.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Li Zhong <zhong@linux.vnet.ibm.com> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-10-13 15:52:44 -07:00
clk: rp1: Add support for clocks provided by RP1 RaspberryPi RP1 is an MFD providing, among other peripherals, several clock generators and PLLs that drives the sub-peripherals. Add the driver to support the clock providers. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Link: https://lore.kernel.org/r/20250529135052.28398-4-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-05-29 15:50:41 +02:00
clk: Add clock driver for the RISC-V RPMI clock service group The RPMI specification defines a clock service group which can be accessed via SBI MPXY extension or dedicated S-mode RPMI transport. Add mailbox client based clock driver for the RISC-V RPMI clock service group. Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Co-developed-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-11-apatel@ventanamicro.com [pjw@kernel.org: converted rpmi_clkrate_u64 macro to a function; replaced bare constant with a macro] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-08-18 09:39:06 +05:30
clk: hi6220: Add the hi655x's pmic clock The hi655x multi function device is a PMIC providing regulators. The PMIC also provides a clock for the WiFi and the Bluetooth, let's implement this clock in order to add it in the hi655x MFD and allow proper wireless initialization. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> [sboyd@codeaurora.org: Remove clkdev usage] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-17 19:19:25 +02:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: various improvements and fixes Here's various improvements and fixes for the clk subsystem that was posted prior to the opening of the last merge window. - Add spread spectrum clock (SSC) support to the clk framework, including a new assigned-clock-sscs devicetree property and clk_hw_set_spread_spectrum() API with KUnit tests (Peng Fan) - Add SCMI clock OEM extensions for the i.MX95 clock driver and introduce a common SCMI clock header (Peng Fan) - Add clock, reset, and devicetree bindings for the ESWIN EIC7700 HSP clock and reset generator (Xuyang Dong) - Add clk_determine_rate_noop() helper for clock drivers that can do any rate, and convert existing open-coded implementations across hisilicon, imx, qcom, renesas, rp1, samsung, scpi, sprd, mediatek phy, and mediatek pmdomain drivers (Brian Masney) - Add kernel-doc documentation for struct clk_core and the core clock flags, and wire up clk identifiers into the documentation build (Brian Masney) - Fix clk_divider_bestdiv() returning the minimum rate instead of the maximum rate for large rate requests, with KUnit tests (Lad Prabhakar) - Fix Nuvoton MA35D1 PLL frequency calculation including ignored div_u64 return values, incorrect PLL_CTL1_FRAC bit field width, and broken determine_rate logic (Joey Lu) - Support unique clock names for multi-socket Tegra platforms (Jon Hunter) - Allow COMPILE_TEST builds for HiSilicon clock drivers (Rosen Penev) - Various fixes and cleanups from Akari Tsuyukusa, Alexander A. Klimov, Brian Masney, David Carlier, David Laight, Min zhang, Myeonghun Pak, Pavel Löbl, Randy Dunlap, Rob Herring, Rosen Penev, Uwe Kleine-König, William Theesfeld, Xuyang Dong, and Yu-Chun Lin Signed-off-by: Brian Masney <bmasney@redhat.com> -----BEGIN PGP SIGNATURE----- iIwEABYKADQWIQSkbTJwWGWqPd7cKQS30t0nXX7AhwUCakLuwRYcbWFzbmV5YkBv bnN0YXRpb24ub3JnAAoJELfS3SddfsCH1qIA/3OYdBm1fIrd/PumuFj/6xnito0J nwY64dzlOm4kPVynAQDGDUxQMevRq8AFXh33kOh+cCFg7H9CXjF55ajB2TXaBg== =1BFM -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmqDNnUUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSU1oxAAiKegvy9n27Avul9t7GX9SYpyM93E XXvr3kdI6ySTkAk/CXqSUKLS0FnqMepQE6b1FSiRQGOyPl0iYxXFKZ3iwd5ZHHIN AWWwXYhzAuwOXNnNzlz3SFJ40lt8zTLY4Y20sG3/+iuIiqotywONWqr1JlUwlgVI ahmGqWPj2qtuKCnxnOQnBNcaA/xd3NqdjHt0W1UgXP9Hn9j0l+EhL7f4TJVp4Wq5 LU+jlA7g6Btxy5JrJOpzdgd84bPNw4xxYOhzn3ek8ULB5H0QRj36cu2ZahNudZJF ObIr23OOgRJLZtKQ/WlM5fHXONuhnE9CSTiBEeXSr2yon0JKcJ8bjKUvTilJhZ34 TV5DSBxB70E0Vs4omJJ0NtKsJWW+zoa53yU2mT88VWQNTDLfTe4VHVbBCBN9cBnV aS8ssQF9uipsOKEGQ1aQG9neV2ML0OXd3nMx9f8VgMcfV5K8Wbtt5oRFtQtl5fS/ uCkTbII+IL29MMVJ6+X3sRilFY8SsKxaG1gDmk50LwcMUVx4hzNGOhQC/1TPRNG2 ZuSEeRX10syBwI5txupnxD1mJClw2ZxE9QmSTmKmWI1Y3aSdcSdtKnEobhLXJmmS 7PFtOe9Rf8lRbYKxZGaW63R/9fOmrf3wyG9kzepLKJl8loV7SRJ8by6psNBfBgVO kyANlk/27dpi1Zo= =QbCr -----END PGP SIGNATURE----- Merge tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile Pull clk patches picked up by Brian Masney: Here's various improvements and fixes for the clk subsystem that was posted prior to the opening of the last merge window. - Add spread spectrum clock (SSC) support to the clk framework, including a new assigned-clock-sscs devicetree property and clk_hw_set_spread_spectrum() API with KUnit tests (Peng Fan) - Add SCMI clock OEM extensions for the i.MX95 clock driver and introduce a common SCMI clock header (Peng Fan) - Add clock, reset, and devicetree bindings for the ESWIN EIC7700 HSP clock and reset generator (Xuyang Dong) - Add clk_determine_rate_noop() helper for clock drivers that can do any rate, and convert existing open-coded implementations across hisilicon, imx, qcom, renesas, rp1, samsung, scpi, sprd, mediatek phy, and mediatek pmdomain drivers (Brian Masney) - Add kernel-doc documentation for struct clk_core and the core clock flags, and wire up clk identifiers into the documentation build (Brian Masney) - Fix clk_divider_bestdiv() returning the minimum rate instead of the maximum rate for large rate requests, with KUnit tests (Lad Prabhakar) - Fix Nuvoton MA35D1 PLL frequency calculation including ignored div_u64 return values, incorrect PLL_CTL1_FRAC bit field width, and broken determine_rate logic (Joey Lu) - Support unique clock names for multi-socket Tegra platforms (Jon Hunter) - Allow COMPILE_TEST builds for HiSilicon clock drivers (Rosen Penev) - Various fixes and cleanups from Akari Tsuyukusa, Alexander A. Klimov, Brian Masney, David Carlier, David Laight, Min zhang, Myeonghun Pak, Pavel Löbl, Randy Dunlap, Rob Herring, Rosen Penev, Uwe Kleine-König, William Theesfeld, Xuyang Dong, and Yu-Chun Lin Signed-off-by: Brian Masney <bmasney@redhat.com> [sboyd@kernel.org: Fix allmodconfig modpost failure in scmi] * tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux: (53 commits) pmdomain: mediatek: mtk-mfg: use clk_determine_rate_noop() pmdomain: mediatek: airoha: use clk_determine_rate_noop() phy: mediatek: phy-mtk-hdmi-mt2701: use clk_determine_rate_noop() clk: sprd: use clk_determine_rate_noop() clk: scpi: use clk_determine_rate_noop() clk: samsung: acpm: use clk_determine_rate_noop() clk: rp1: use clk_determine_rate_noop() clk: renesas: rzg2l-cpg: use clk_determine_rate_noop() clk: qcom: smd-rpm: use clk_determine_rate_noop() clk: qcom: rpmh: use clk_determine_rate_noop() clk: qcom: rpm: use clk_determine_rate_noop() clk: imx: scu: use clk_determine_rate_noop() clk: hisilicon: hi3660-stub: use clk_determine_rate_noop() clk: add clk_determine_rate_noop() clk: imx: scu: drop redundant init.ops variable assignment clk: test: convert constants to use HZ_PER_MHZ docs: clk: include some identifiers to keep documentation up to date clk: add kernel docs for struct clk_core clk: add kernel docs for the core flags clk: hisilicon: allow COMPILE_TEST builds ...
2026-08-13 17:17:13 -07:00
clk: add support for clocks provided by SCP(System Control Processor) On some ARM based systems, a separate Cortex-M based System Control Processor(SCP) provides the overall power, clock, reset and system control. System Control and Power Interface(SCPI) Message Protocol is defined for the communication between the Application Cores(AP) and the SCP. This patch adds support for the clocks provided by SCP using SCPI protocol. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@baylibre.com> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Jon Medhurst (Tixy) <tixy@linaro.org> Cc: linux-clk@vger.kernel.org
2015-03-30 10:59:52 +01:00
clk: Add Si5341/Si5340 driver Adds a driver for the Si5341 and Si5340 chips. The driver does not fully support all features of these chips, but allows the chip to be used without any support from the "clockbuilder pro" software. If the chip is preprogrammed, that is, you bought one with some defaults burned in, or you programmed the NVM in some way, the driver will just take over the current settings and only change them on demand. Otherwise the input must be a fixed XTAL in its most basic configuration (no predividers, no feedback, etc.). The driver supports dynamic changes of multisynth, output dividers and enabling or powering down outputs and multisynths. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> [sboyd@kernel.org: Mark some things static, use BIT_ULL for big bits and ULL for big constants] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-17 15:23:52 +02:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
Add driver for the si514 clock generator chip This patch adds the driver and devicetree documentation for the Silicon Labs SI514 clock generator chip. This is an I2C controlled oscillator capable of generating clock signals ranging from 100kHz to 250MHz. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> [sboyd@codeaurora.org: Drop clk.h include, remove some casts] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-02 09:15:29 +02:00
clk: Add driver for the si544 clock generator chip This patch adds the driver and devicetree documentation for the Silicon Labs SI544 clock generator chip. This is an I2C controlled oscillator capable of generating clock signals ranging from 200kHz to 1500MHz. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> [sboyd: assign max_freq to 0 in is_valid_frequency() to squelch warning] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 09:15:41 +01:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: Add Sunplus SP7021 clock driver Add clock driver for Sunplus SP7021 SoC. Signed-off-by: Qin Jian <qinjian@cqplus1.com> Link: https://lore.kernel.org/r/20221219015130.42621-1-qinjian@cqplus1.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-12-19 09:51:30 +08:00
clk: stm32: add configuration flags for each of the stm32 drivers Add two configuration flags to be able to not compile all the time stm32f and stm32h7 drivers when ARCH_STM32 is set. That help to save some space on those small platforms. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-12 10:32:48 +01:00
clk: Introduce clk-tps68470 driver The TPS68470 PMIC provides Clocks, GPIOs and Regulators. At present in the kernel the Regulators and Clocks are controlled by an OpRegion driver designed to work with power control methods defined in ACPI, but some platforms lack those methods, meaning drivers need to be able to consume the resources of these chips through the usual frameworks. This commit adds a driver for the clocks provided by the tps68470, and is designed to bind to the platform_device registered by the intel_skl_int3472 module. This is based on this out of tree driver written by Intel: https://github.com/intel/linux-intel-lts/blob/4.14/base/drivers/clk/clk-tps68470.c with various cleanups added. Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20211203102857.44539-7-hdegoede@redhat.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-12-03 11:28:49 +01:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: twl: add clock driver for TWL6032 The TWL6032 has some clock outputs which are controlled like fixed-voltage regulators, in some drivers for these chips found in the wild, just the regulator api is abused for controlling them, so simply use something similar to the regulator functions. Due to a lack of hardware available for testing, leave out the TWL6030-specific part of those functions. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://lore.kernel.org/r/20230916100515.1650336-5-andreas@kemnade.info Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-09-16 12:05:14 +02:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: rs9: Add Renesas 9-series PCIe clock generator driver Add driver for Renesas 9-series PCIe clock generators. This driver is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C PCIe clock generators, currently the only tested and supported chip is 9FGV0241. The driver is capable of configuring per-chip spread spectrum mode and output amplitude, as well as per-output slew rate. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20220226040723.143705-3-marex@denx.de [sboyd@kernel.org: Use non-underscore API for fixed factor] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-02-26 05:07:23 +01:00
clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators Add driver for the Skyworks Si521xx PCIe clock generators. Supported models are Si52144/Si52146/Si52147, tested model is Si52144. It should be possible to add Si5213x series as well. Signed-off-by: Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20230118191521.15544-2-marex@denx.de [sboyd@kernel.org: Make clk_ops const] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-18 20:15:21 +01:00
clk: Add support for versa3 clock driver Add support for Renesas versa3 clock driver(5p35023). The clock generator provides 6 output clocks. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20230705171000.85786-3-biju.das.jz@bp.renesas.com [sboyd@kernel.org: Add newline to printk] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-07-05 18:10:00 +01:00
clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933 Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These chips have two clock inputs, XTAL or CLK, which are muxed into single PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip while the 5P49V5923 requires external XTAL. The PLL feeds two fractional dividers. Each fractional divider feeds output mux, which allows selecting between clock from the fractional divider itself or from output mux on output N-1. In case of output mux 0, the output N-1 is instead connected to the output from the mux feeding the PLL. The driver thus far supports only the 5P49V5923 and 5P49V5933, while it should be easily extensible to the whole 5P49V59xx family of chips as they are all pretty similar. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-12 02:03:24 +01:00
clk: Renesas versaclock7 ccf device driver Renesas Versaclock7 is a family of configurable clock generator ICs with fractional and integer dividers. This driver has basic support for the RC21008A device, a clock synthesizer with a crystal input and 8 outputs. The supports changing the FOD and IOD rates, and each output can be gated. Signed-off-by: Alex Helms <alexander.helms.jy@renesas.com> Link: https://lore.kernel.org/r/20220912183613.22213-3-alexander.helms.jy@renesas.com Tested-by: Saeed Nowshadi <saeed.nowshadi@amd.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-12 11:36:13 -07:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: Makefile: re-sort and clean up Sorting is hard. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-15 17:09:25 -07:00
clk: actions: Add common clock driver support Add support for Actions Semi common clock driver with generic structures and interface functions. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-26 23:08:57 +05:30
clk: analogbits: add Wide-Range PLL library Add common library code for the Analog Bits Wide-Range PLL (WRPLL) IP block, as implemented in TSMC CLN28HPC. There is no bus interface or register target associated with this PLL. This library is intended to be used by drivers for IP blocks that expose registers connected to the PLL configuration and status signals. Based on code originally written by Wesley Terpstra <wesley@sifive.com>: https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 This version incorporates several changes requested by Stephen Boyd <sboyd@kernel.org>. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Wesley Terpstra <wesley@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Megan Wachs <megan@sifive.com> Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org [sboyd@kernel.org: Fix some const issues] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-30 13:50:58 -07:00
clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory. Prepare for long-term maintenance and future additions by introducing a dedicated drivers/clk/aspeed/ subdirectory for ASPEED clock drivers. Move the existing ASPEED clock drivers into the new drivers/clk/aspeed/ subdirectory. No functional change, file move only. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-12-24 13:37:22 +08:00
The second half of the clock framework pull requeust for 3.14 is dominated by platform support for Qualcomm's MSM SoCs, DT binding updates for TI's OMAP-ish processors and additional support for Samsung chips. Additionally there are other smaller clock driver changes and several last minute fixes. This pull request also includes the HiSilicon support that depends on the already-merged arm-soc pull request. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJS5tJoAAoJEDqPOy9afJhJg2YP/1hZueLNwJwtasgSlrjPAKai +VDc1Sn0lB7p0D0r0cyd6kUPlAMBwZOMJ3wLvbI+z/yItCfXNxIDpaQszMoHmBox Dgj3BmnM0GJgtE124qKynFdDqJ09aHcJZ9iEXQAxwo3mWvmHW8U2P2nDQJbxz3Qm i/F7KzpXk6seUV7f14doPD0PY5CVRm0p5dfMXLsroLvWjrvTqA4imbAuOeHI1UuG siboNe94nLcAj8iBQanugpKjlKT4+jjeTCfCuJ2OeS5o2Lz3KO2BYr6HekbsNZiz atydhPO840fCNxR/SSKAgIzr9FjQ5Q2fJvF7m+6XyFND9gZ/yjN14LdlTU1SX3kD 1yB8OSqKjjLOBU5P1UwvD8NL8kldwoynYT7T4JqYIZQHZyjNGToBZ1SzUZ/yVsnE sMbfVC8X5RMEJzGIWNbm6kz+37CRQWNn4aPghGjkyLDGpyVf7dn+jlGBgGiahb8g io1Ir35/FykHAVx16veYD09sB+VYAeD23P/nuP7MbdCzYLmu4ibAiJyBiPQvcxmq YZWENS2j4NvG2XdHW07SpWC0U0mr5MLOkFjVkcW8h+aaT3FJUwaP0wjRyWoaF3Dt sEZ10OJLuXK5x3oiLFhuqHwGSGy+XoIq3FL00jjkib6uKcv2hNYQ+ZpPzG/CDbNx ndMT57cycXMYrOp8jklw =WRJD -----END PGP SIGNATURE----- Merge tag 'clk-for-linus-3.14-part2' of git://git.linaro.org/people/mike.turquette/linux Pull more clock framework changes from Mike Turquette: "The second half of the clock framework pull requeust for 3.14 is dominated by platform support for Qualcomm's MSM SoCs, DT binding updates for TI's OMAP-ish processors and additional support for Samsung chips. Additionally there are other smaller clock driver changes and several last minute fixes. This pull request also includes the HiSilicon support that depends on the already-merged arm-soc pull request" [ Fix up stupid compile error in the source tree with evil merge - Grumpy Linus ] * tag 'clk-for-linus-3.14-part2' of git://git.linaro.org/people/mike.turquette/linux: (49 commits) clk: sort Makefile clk: sunxi: fix overflow when setting up divided factors clk: Export more clk-provider functions dt-bindings: qcom: Fix warning with duplicate dt define clk: si5351: remove variant from platform_data clk: samsung: Remove unneeded semicolon clk: qcom: Fix modular build ARM: OMAP3: use DT clock init if DT data is available ARM: AM33xx: remove old clock data and link in new clock init code ARM: AM43xx: Enable clock init ARM: OMAP: DRA7: Enable clock init ARM: OMAP4: remove old clock data and link in new clock init code ARM: OMAP2+: io: use new clock init API ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT ARM: OMAP3: hwmod: initialize clkdm from clkdm_name ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm ARM: OMAP2+: clock: use driver API instead of direct memory read/write ARM: OMAP2+: clock: add support for indexed memmaps ARM: dts: am43xx clock data ARM: dts: AM35xx: use DT clock data ...
2014-01-28 18:44:53 -08:00
clk: add artpec-6 clock controller Add a driver for the main clock controller of the Artpec-6 Soc. Signed-off-by: Lars Persson <larper@axis.com> [sboyd@codeaurora.org: Reformatted driver structure and of match] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-04 11:23:23 +02:00
clk: Makefile: re-sort and clean up Sorting is hard. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-15 17:09:25 -07:00
clk: ns2: add clock support for Broadcom Northstar 2 SoC The Broadcom Northstar 2 SoC is architected under the iProc architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, LCPLL DDR, LCPLL Ports, all derived from an onboard crystal. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-15 15:48:31 -04:00
clk: berlin: add driver for BG2x audio/video PLL This is a driver for the AVPLLs built upon a VCO with 8 channels each found on Marvell Berlin2 SoCs. While both VCOs found on BG2/BG2CD share the same register set, sometimes registers shifts for one of the VCOs are a bit off. Nothing serious that should require a separate driver, so deal with both VCOs in a single driver instead. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-19 18:43:24 +02:00
clk: cix: add sky1 audss clock controller Add a platform driver for the Cix Sky1 AUDSS CRU. The driver maps the CRU registers and registers mux, divider and gate clocks for DSP, SRAM, HDA, DMAC, I2S, mailbox, watchdog and timer blocks. Four SoC-level audio reference clocks are enabled as inputs to the internal clock tree. The driver releases the AUDSS NOC reset, enables runtime PM and instantiates the auxiliary reset device. Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-07-23 17:08:06 +08:00
clk: davinci: New driver for davinci PLL clocks This adds a new driver for mach-davinci PLL clocks. This is porting the code from arch/arm/mach-davinci/clock.c to the common clock framework. Additionally, it adds device tree support for these clocks. The ifeq ($(CONFIG_COMMON_CLK), y) in the Makefile is needed to prevent compile errors until the clock code in arch/arm/mach-davinci is removed. Note: although there are similar clocks for TI Keystone we are not able to share the code for a few reasons. The keystone clocks are device tree only and use legacy one-node-per-clock bindings. Also the register layouts are a bit different, which would add even more if/else mess to the keystone clocks. And the keystone PLL driver doesn't support setting clock rates. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-15 21:52:18 -05:00
clk: eswin: Add eic7700 clock driver Add clock drivers for the EIC7700 SoC. The clock controller on the ESWIN EIC7700 provides various clocks to different IP blocks within the SoC. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # ebc77 Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> Tested-by: Bo Gan <ganboing@gmail.com> # hfp550 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-03-03 16:07:12 +08:00
clk: hisilicon: allow COMPILE_TEST builds The HiSilicon clock symbols already depend on ARCH_HISI or COMPILE_TEST, but the parent clock Makefile only descends into the hisilicon directory when ARCH_HISI is enabled. Add a hidden family gate selected by the HiSilicon clock and reset symbols, default it for ARCH_HISI, and use it for the parent Makefile descent. This keeps existing platform builds unchanged while allowing compile-test coverage. Tested with: make LLVM=1 ARCH=loongarch drivers/clk/hisilicon/ Assisted-by: Codex:GPT-5.5 Signed-off-by: Rosen Penev <rosenp@gmail.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-05-08 22:11:10 -07:00
clk: boston: Add a driver for MIPS Boston board clocks Add a driver for the clocks provided by the MIPS Boston board from Imagination Technologies. 2 clocks are provided - the system clock & the CPU clock - and each is a simple fixed rate clock whose frequency can be determined by reading a register provided by the board. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-06-17 13:52:47 -07:00
clk: imx: add configuration option for mmio clks The patch introduces CONFIG_MXC_CLK option for legacy MMIO clocks, this is required to compile legacy MMIO clock conditionally when adding SCU based clocks for MX8 platforms later. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-13 15:42:50 +00:00
clk: ingenic: Add proper Kconfig entries Previously, the CGU code corresponding to the SoC for which we're compiling the kernel was the only one enabled, which made it impossible to build one kernel that supports them all. Now, it is possible to select more than one SoC to support. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 15:17:41 +02:00
clk: keystone: fix compile testing Some keystone clock drivers can be selected when COMPILE_TEST is enabled but since commit b745c0794e2f ("clk: keystone: Add sci-clk driver support") they are never actually built. Enable compile testing by allowing the build system to process the keystone drivers. Fixes: b745c0794e2f ("clk: keystone: Add sci-clk driver support") Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-11-27 14:53:25 +01:00
clk: mediatek: fixup test-building of MediaTek clock drivers Let the build system looking into the directiory where the clock drivers resides for the COMPILE_TEST alternative dependency allows test-building the drivers. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-20 14:42:59 +08:00
clk: meson: use CONFIG_ARCH_MESON to enter meson clk directory Use CONFIG_ARCH_MESON to let make enter the meson clock directory. As part of a rework, CONFIG_COMMON_CLK_AMLOGIC is about to be removed. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201125841.26785-3-jbrunet@baylibre.com
2019-02-01 13:58:39 +01:00
clk: microchip: Add driver for Microchip PolarFire SoC Add support for clock configuration on Microchip PolarFire SoC Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org> Co-developed-by: Padmarao Begari <padmarao.begari@microchip.com> Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Co-developed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220222121143.3316880-2-conor.dooley@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-02-22 12:11:44 +00:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: mstar: Allow MStar clk drivers to be compile tested Allow COMPILE_TEST to also build the MStar clk drivers instead of only building them when ARCH_MSTARV7 is selected. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Suggested-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210215115710.3762276-1-daniel@0x0f.com [sboyd@kernel.org: Drop regmap select too] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-15 20:57:09 +09:00
clk: unconditionally recurse into clk/mvebu/ The drivers/clk/mvebu directory is only being built when CONFIG_PLAT_ORION=y. As we are going to support additional mvebu platforms in drivers/clk/mvebu, which don't have CONFIG_PLAT_ORION=y, we need to recurse into this directory regardless of the value of CONFIG_PLAT_ORION. Since all files in drivers/clk/mvebu/ are already conditionally compiled depending on various Kconfig options, we can recurse unconditionally into drivers/clk/mvebu without any other change. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-27 11:26:13 +02:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: nuvoton: Add clock driver for ma35d1 clock controller The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. This driver support ma35d1 clock gating, divider, and individual PLL configuration. There are 6 PLLs in ma35d1 SoC: - CA-PLL for the two Cortex-A35 CPU clock - SYS-PLL for system bus, which comes from the companion MCU and cannot be programmed by clock controller. - DDR-PLL for DDR - EPLL for GMAC and GFX, Display, and VDEC IPs. - VPLL for video output pixel clock - APLL for SDHC, I2S audio, and other IPs. CA-PLL has only one operation mode. DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3 operation modes: integer mode, fraction mode, and spread specturm mode. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-05 04:07:47 +00:00
clk: lpc18xx: add NXP specific COMMON_CLK_NXP configuration symbol The change adds COMMON_CLK_NXP configuration symbol and enables it for NXP LPC18XX architecture, this is needed to reuse drivers/clk/nxp folder for NXP common clock framework drivers other than LPC18XX one. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-06 12:45:56 +02:00
clk: pistachio: Make it selectable for generic MIPS kernel We're moving pistachio to generic MIPS kernel. The clk driver should be avilable to the generic MIPS kernel. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-07-23 10:25:37 +08:00
clk: pxa clocks build system fix Fix the building of pxa clock drivers so that the files are actually compiled if and only if COMMON_CLK was selected by the architecture. This prevents conflicts with mach-pxa clock legacy implementation. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-10-01 23:39:29 +02:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: ralink: add clock driver for mt7621 SoC The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or some ip cores. Looking into driver code, and some openWRT patched there are another frequencies which are used in some drivers (uart, sd...). According to all of this information the clock plan for this SoC is set as follows: - Main top clock "xtal" from where all the rest of the world is derived. - CPU clock "cpu" derived from "xtal" frequencies and a bunch of register reads and predividers. - BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz. - Fixed clocks from "xtal": * "50m": 50 MHz. * "125m": 125 MHz. * "150m": 150 MHz. * "250m": 250 MHz. * "270m": 270 MHz. We also have a buch of gate clocks with their parents: * "hsdma": "150m" * "fe": "250m" * "sp_divtx": "270m" * "timer": "50m" * "pcm": "270m" * "pio": "50m" * "gdma": "bus" * "nand": "125m" * "i2c": "50m" * "i2s": "270m" * "spi": "bus" * "uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m" * "shxc": "50m" With this information the clk driver will provide clock and gates functionality from a a set of hardcoded clocks allowing to define a nice device tree without fixed clocks. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210410055059.13518-2-sergio.paracuellos@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-04-10 07:50:56 +02:00
clk: renesas: Rework Kconfig and Makefile logic The goals are to: - Allow precise control over and automatic selection of which (sub)drivers are used for which SoC (which may change in the future), - Allow adding support for new SoCs easily, - Allow compile-testing of all (sub)drivers, - Keep driver selection logic in the subsystem-specific Kconfig, independent from the architecture-specific Kconfig (i.e. no "select" from arch/arm64/Kconfig.platforms), to avoid dependencies. This is implemented by: - Introducing Kconfig symbols for all drivers and sub-drivers, - Introducing the Kconfig symbol CLK_RENESAS, which is enabled automatically when building for a Renesas ARM platform, and which enables all required drivers without interaction of the user, based on SoC-specific ARCH_* symbols, - Allowing the user to enable any Kconfig symbol manually if COMPILE_TEST is enabled, - Using the new Kconfig symbols instead of the ARCH_* symbols to control compilation in the Makefile, - Always entering drivers/clk/renesas/ during the build. Note that currently not all (sub)drivers are enabled for compile-testing, as they depend on independent fixes in other subsystems. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-24 16:54:14 +02:00
clk: rockchip: allow COMPILE_TEST builds COMMON_CLK_ROCKCHIP already gates the Rockchip clock objects inside the Rockchip clock Makefile. Allow selecting it for COMPILE_TEST and use it for the parent Makefile descent instead of ARCH_ROCKCHIP. The per-SoC Rockchip clock symbols already have COMPILE_TEST dependencies, so this exposes the existing build coverage to other architectures without selecting the Rockchip platform. Tested with: make LLVM=1 ARCH=loongarch drivers/clk/rockchip/ Assisted-by: Codex:GPT-5.5 Signed-off-by: Rosen Penev <rosenp@gmail.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/20260509003602.956186-1-rosenp@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2026-05-08 17:36:02 -07:00
drivers: clk: use COMMON_CLK_SAMSUNG for Samsung clock support This patch replaces PLAT_SAMSUNG with COMMON_CLK_SAMSUNG for Samsung common clock support. Any Samsung SoC want to use Samsung common clock infrastructure can simply select COMMON_CLK_SAMSUNG. CC: Mike Turquette <mturquette@linaro.org> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-08 13:07:11 +09:00
clk: sifive: add a driver for the SiFive FU540 PRCI IP block Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com>: https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. This version includes several changes requested by Stephen Boyd <sboyd@kernel.org>. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Wesley W. Terpstra <wesley@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Megan Wachs <megan@sifive.com> Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-clk@vger.kernel.org [sboyd@kernel.org: Fix some const and ARRAY_SIZE() issues, make makefile only descend if CLK_SIFIVE=y] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-30 13:51:00 -07:00
clk: socfpga: allow compile testing of Stratix 10 / Agilex clocks The Stratix 10 / Agilex / N5X clocks do not use anything other than OF or COMMON_CLK so they should be compile testable on most of the platforms. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-03-11 16:27:07 +01:00
clk: sophgo: Add clock support for CV1800 SoC Add clock definition and driver code for CV1800 SoC. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV180X-Clock-v1.xlsx Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf Link: https://lore.kernel.org/r/IA1PR20MB49534F37F802CAF117364D66BB262@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-03-09 17:02:52 +08:00
clk: spacemit: Add clock support for SpacemiT K1 SoC The clock tree of K1 SoC contains three main types of clock hardware (PLL/DDN/MIX) and has control registers split into several multifunction devices: APBS (PLLs), MPMU, APBC and APMU. All register operations are done through regmap to ensure atomicity between concurrent operations of clock driver and reset, power-domain driver that will be introduced in the future. Signed-off-by: Haylen Chu <heylenay@4d2.org> Reviewed-by: Alex Elder <elder@riscstar.com> Reviewed-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250416135406.16284-4-heylenay@4d2.org Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-04-16 13:54:03 +00:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: sprd: fix compile-testing I got a build failure with CONFIG_ARCH_SPRD=m when the main portion of the clock driver failed to get linked into the kernel: ERROR: modpost: "sprd_pll_sc_gate_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined! ERROR: modpost: "sprd_pll_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined! ERROR: modpost: "sprd_div_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined! ERROR: modpost: "sprd_comp_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined! ERROR: modpost: "sprd_mux_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined! ERROR: modpost: "sprd_gate_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined! ERROR: modpost: "sprd_sc_gate_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined! ERROR: modpost: "sprd_clk_probe" [drivers/clk/sprd/sc9863a-clk.ko] undefined! ERROR: modpost: "sprd_clk_regmap_init" [drivers/clk/sprd/sc9863a-clk.ko] undefined! ERROR: modpost: "sprd_pll_ops" [drivers/clk/sprd/sc9860-clk.ko] undefined! ERROR: modpost: "sprd_div_ops" [drivers/clk/sprd/sc9860-clk.ko] undefined! ERROR: modpost: "sprd_mux_ops" [drivers/clk/sprd/sc9860-clk.ko] undefined! This is a combination of two trivial bugs: - A platform should not be 'tristate', it should be a 'bool' symbol like the other platforms, if only for consistency, and to avoid surprises like this one. - The clk Makefile does not traverse into the sprd subdirectory if the platform is disabled but the drivers are enabled for compile-testing. Fixing either of the two would be sufficient to address the link failure, but for correctness, both need to be changed. Fixes: 2b1b799d7630 ("arm64: change ARCH_SPRD Kconfig to tristate") Fixes: d41f59fd92f2 ("clk: sprd: Add common infrastructure") Acked-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-04-07 16:21:46 +02:00
clk: st: Support for DIVMUX and PreDiv Clocks The patch supports the DIVMUX and PreDiv clocks used by ClockGenA(s) DIVMUX clock : Divider-Multiplexer-Gate inside ClockGenA(s) It includes support for each channel : 3-parent Multiplexer, Divider for each Parent, Gate to switch OFF the output channel. The clock is implemented using generic clocks implemented in the kernel clk_divider and clk_mux. PreDiv clock : Fixed Divider Clock used inside ClockGenA(s) to divide the oscillator clock by factor-of-16. The clock is implemented using generic clocks implemented in the kernel clk_divider. Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-27 16:24:14 +01:00
clk: stm32: allow STM32MP COMPILE_TEST builds COMMON_CLK_STM32MP already allows COMPILE_TEST, but the parent clock Makefile only descends into drivers/clk/stm32 for ARCH_STM32. Use the STM32MP clock symbol for that directory gate instead. Tested with: make LLVM=1 ARCH=loongarch drivers/clk/stm32/ Assisted-by: Codex:GPT-5.5 Signed-off-by: Rosen Penev <rosenp@gmail.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-07-19 14:50:40 -07:00
clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Using ARCH_FOO symbol is preferred than SOC_FOO. Set obj-y for starfive/ in Makefile, so the StarFive drivers can be compiled with COMPILE_TEST=y but ARCH_STARFIVE=n. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-01 19:19:15 +08:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: sunxi-ng: Allow the CCU core to be built as a module Like the individual CCU drivers, it can be beneficial for memory consumption of cross-platform configurations to only load the CCU core on the relevant platform. For example, a generic arm64 kernel sees the following improvement when building the CCU core and drivers as modules: before: text data bss dec hex filename 13882360 5251670 360800 19494830 12977ae vmlinux after: text data bss dec hex filename 13734787 5086442 360800 19182029 124b1cd vmlinux So the result is a 390KB total reduction in kernel image size. The one early clock provider (sun5i) requires the core to be built in. Now that loading the MMC driver will trigger loading the CCU core, the MMC timing mode functions do not need a compile-time fallback. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119033338.25486-5-samuel@sholland.org
2021-11-18 21:33:37 -06:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: tenstorrent: Add Atlantis clock controller driver Add driver for clock controller in Tenstorrent Atlantis SoC. This version of the driver covers clocks from RCPU subsystem. 5 types of clocks generated by this controller: PLLs (PLLs with bypass functionality and an additional Gate clk at output), Shared Gates (Multiple Gate clks that share an enable bit), standard Muxes, Dividers and Gates. All clocks are implemented using custom clk ops and use the regmap interface associated with the syscon. All clocks are derived from a 24 Mhz oscillator. The reset controller is also setup as an auxiliary device of the clock controller. Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Drew Fustini <fustini@kernel.org> Signed-off-by: Drew Fustini <fustini@kernel.org>
2026-03-06 11:12:19 -06:00
clk: thead: allow COMPILE_TEST builds Follow the pattern of many other directories in this Makefile (sunxi-ng, tenstorrent, ti, etc.) by using obj-y. This allows COMPILE_TEST to select the driver without having CONFIG_ARCH_THEAD enabled Tested with: make LLVM=1 ARCH=loongarch drivers/clk/thead/ Assisted-by: Codex:GPT-5.5 Acked-by: Drew Fustini <fustini@kernel.org> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Rosen Penev <rosenp@gmail.com> Signed-off-by: Drew Fustini <fustini@kernel.org>
2026-07-06 17:56:19 -07:00
clk: ti: Allow COMPILE_TEST to build selected drivers The arch independent drivers can be build testeed with COMPILE_TEST. Let's allow that for drivers/clk/ti. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-02-26 09:45:03 -08:00
clk: ultrarisc: Add DP1000 clock driver Add a clock driver for the UltraRISC DP1000 SoC. The clock tree is driven by a SYSPLL and provides fixed-factor clocks for the subsystem and PCIe, divider-based root clocks for GMAC and the UART, I2C, and SPI blocks, and per-instance gate clocks for UART0-3, I2C0-3, and SPI0-1. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-07-20 08:38:06 +08:00
clk: uniphier: add core support code for UniPhier clock driver This includes UniPhier clock driver code, except SoC-specific data arrays. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16 16:40:03 +09:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: versatile: Rework kconfig structure CONFIG_COMMON_CLK_VERSATILE doesn't really do anything other than hiding Arm Ltd reference platform clock drivers. It is both selected by the platforms that need it and has a 'depends on' for those platforms. Let's drop the selects and convert CONFIG_COMMON_CLK_VERSATILE into a menuconfig entry. With this make CONFIG_ICST visible. Move the 'select REGMAP_MMIO' to the drivers that require it (SP810 did not). This also has the side effect of enabling CONFIG_ICST for COMPILE_TEST as it was not visible before. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
2020-04-29 15:58:13 -05:00
clk: visconti: Add support common clock driver and reset driver Add support for common interface of the common clock and reset driver for Toshiba Visconti5 and its SoC, TMPV7708. The PIPLLCT provides the PLL, and the PISMU provides clock and reset functionality. Each drivers are provided in this patch. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Link: https://lore.kernel.org/r/20211025031038.4180686-4-nobuhiro1.iwamatsu@toshiba.co.jp [sboyd@kernel.org: Add bitfield.h include to pll.c] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-25 12:10:37 +09:00
clk: Make x86/ conditional on CONFIG_COMMON_CLK Fix Makefile for x86 support, dependency on CONFIG_COMMON_CLK was not explicit Fixes: 701190fd7419 ('clk: x86: add support for Lynxpoint LPSS clocks') Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-23 12:07:41 -06:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
clk: Make x86/ conditional on CONFIG_COMMON_CLK Fix Makefile for x86 support, dependency on CONFIG_COMMON_CLK was not explicit Fixes: 701190fd7419 ('clk: x86: add support for Lynxpoint LPSS clocks') Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-23 12:07:41 -06:00
clk: xilinx: move xlnx_vcu clock driver from soc The xlnx_vcu driver is actually a clock controller driver which provides clocks that can be used by a driver for the encoder/decoder units. There is no reason to keep this driver in soc. Move the driver to clk. NOTE: The register mapping actually contains registers for AXI performance monitoring, but these are not used by the driver. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-16-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-01-21 08:16:59 +01:00
clk: sort Makefile Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 13:04:49 -08:00
drivers: clk: Add ZynqMP clock driver This patch adds CCF compliant clock driver for ZynqMP. Clock driver queries supported clock information from firmware and regiters pll and output clocks with CCF. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Tejas Patel <tejasp@xilinx.com> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Acked-by: Olof Johansson <olof@lixom.net> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-08 11:21:46 -07:00