2017-12-27 12:55:14 -06:00
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2016-06-15 08:32:18 -05:00
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2012-04-11 17:30:11 +00:00
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2018-03-15 02:15:52 +08:00
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2010-06-08 07:48:09 -06:00
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2018-03-15 02:15:54 +08:00
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2010-06-08 07:48:10 -06:00
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2010-06-08 07:48:09 -06:00
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2024-09-05 09:46:01 +02:00
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2016-05-11 17:34:51 -05:00
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2010-06-08 07:48:10 -06:00
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2014-09-29 15:29:21 +01:00
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2010-06-08 07:48:10 -06:00
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2020-09-17 18:43:40 +02:00
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2010-06-08 07:48:09 -06:00
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2025-01-29 14:35:27 +01:00
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2025-01-09 21:26:59 +08:00
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2019-07-02 18:42:39 +01:00
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2010-06-08 07:48:10 -06:00
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2012-10-08 19:41:58 -05:00
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2023-10-26 08:53:59 -05:00
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2012-10-08 19:41:58 -05:00
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2023-10-26 08:53:58 -05:00
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2010-12-01 10:54:46 +01:00
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2010-06-08 07:48:10 -06:00
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2012-10-08 19:41:58 -05:00
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2023-10-26 08:53:59 -05:00
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2010-06-08 07:48:10 -06:00
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2023-10-26 08:53:59 -05:00
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2010-06-08 07:48:10 -06:00
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2023-10-26 08:53:59 -05:00
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2010-06-08 07:48:10 -06:00
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2021-06-16 11:27:45 +02:00
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2010-06-08 07:48:10 -06:00
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2012-10-08 19:41:58 -05:00
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2010-06-08 07:48:10 -06:00
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2010-06-08 07:48:11 -06:00
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2010-06-08 07:48:10 -06:00
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2023-03-28 15:15:58 -05:00
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2010-12-01 10:54:46 +01:00
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2010-06-08 07:48:10 -06:00
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of: address: Fix address translation when address-size is greater than 2
With the recent addition of of_pci_prop_ranges() in commit 407d1a51921e
("PCI: Create device tree node for bridge"), the ranges property can
have a 3 cells child address, a 3 cells parent address and a 2 cells
child size.
A range item property for a PCI device is filled as follow:
<BAR_nbr> 0 0 <phys.hi> <phys.mid> <phys.low> <BAR_sizeh> <BAR_sizel>
<-- Child --> <-- Parent (PCI definition) --> <- BAR size (64bit) -->
This allow to translate BAR addresses from the DT. For instance:
pci@0,0 {
#address-cells = <0x03>;
#size-cells = <0x02>;
device_type = "pci";
compatible = "pci11ab,100", "pciclass,060400", "pciclass,0604";
ranges = <0x82000000 0x00 0xe8000000
0x82000000 0x00 0xe8000000
0x00 0x4400000>;
...
dev@0,0 {
#address-cells = <0x03>;
#size-cells = <0x02>;
compatible = "pci1055,9660", "pciclass,020000", "pciclass,0200";
/* Translations for BAR0 to BAR5 */
ranges = <0x00 0x00 0x00 0x82010000 0x00 0xe8000000 0x00 0x2000000
0x01 0x00 0x00 0x82010000 0x00 0xea000000 0x00 0x1000000
0x02 0x00 0x00 0x82010000 0x00 0xeb000000 0x00 0x800000
0x03 0x00 0x00 0x82010000 0x00 0xeb800000 0x00 0x800000
0x04 0x00 0x00 0x82010000 0x00 0xec000000 0x00 0x20000
0x05 0x00 0x00 0x82010000 0x00 0xec020000 0x00 0x2000>;
...
pci-ep-bus@0 {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "simple-bus";
/* Translate 0xe2000000 to BAR0 and 0xe0000000 to BAR1 */
ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
0xe0000000 0x01 0x00 0x00 0x1000000>;
...
};
};
};
During the translation process, the "default-flags" map() function is
used to select the matching item in the ranges table and determine the
address offset from this matching item.
This map() function simply calls of_read_number() and when address-size
is greater than 2, the map() function skips the extra high address part
(ie part over 64bit). This lead to a wrong matching item and a wrong
offset computation.
Also during the translation itself, the extra high part related to the
parent address is not present in the translated address.
Fix the "default-flags" map() and translate() in order to take into
account the child extra high address part in map() and the parent extra
high address part in translate() and so having a correct address
translation for ranges patterns such as the one given in the example
above.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Link: https://lore.kernel.org/r/20231017110221.189299-2-herve.codina@bootlin.com
Signed-off-by: Rob Herring <robh@kernel.org>
2023-10-17 13:02:16 +02:00
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2023-10-26 08:53:59 -05:00
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|
of: address: Fix address translation when address-size is greater than 2
With the recent addition of of_pci_prop_ranges() in commit 407d1a51921e
("PCI: Create device tree node for bridge"), the ranges property can
have a 3 cells child address, a 3 cells parent address and a 2 cells
child size.
A range item property for a PCI device is filled as follow:
<BAR_nbr> 0 0 <phys.hi> <phys.mid> <phys.low> <BAR_sizeh> <BAR_sizel>
<-- Child --> <-- Parent (PCI definition) --> <- BAR size (64bit) -->
This allow to translate BAR addresses from the DT. For instance:
pci@0,0 {
#address-cells = <0x03>;
#size-cells = <0x02>;
device_type = "pci";
compatible = "pci11ab,100", "pciclass,060400", "pciclass,0604";
ranges = <0x82000000 0x00 0xe8000000
0x82000000 0x00 0xe8000000
0x00 0x4400000>;
...
dev@0,0 {
#address-cells = <0x03>;
#size-cells = <0x02>;
compatible = "pci1055,9660", "pciclass,020000", "pciclass,0200";
/* Translations for BAR0 to BAR5 */
ranges = <0x00 0x00 0x00 0x82010000 0x00 0xe8000000 0x00 0x2000000
0x01 0x00 0x00 0x82010000 0x00 0xea000000 0x00 0x1000000
0x02 0x00 0x00 0x82010000 0x00 0xeb000000 0x00 0x800000
0x03 0x00 0x00 0x82010000 0x00 0xeb800000 0x00 0x800000
0x04 0x00 0x00 0x82010000 0x00 0xec000000 0x00 0x20000
0x05 0x00 0x00 0x82010000 0x00 0xec020000 0x00 0x2000>;
...
pci-ep-bus@0 {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "simple-bus";
/* Translate 0xe2000000 to BAR0 and 0xe0000000 to BAR1 */
ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
0xe0000000 0x01 0x00 0x00 0x1000000>;
...
};
};
};
During the translation process, the "default-flags" map() function is
used to select the matching item in the ranges table and determine the
address offset from this matching item.
This map() function simply calls of_read_number() and when address-size
is greater than 2, the map() function skips the extra high address part
(ie part over 64bit). This lead to a wrong matching item and a wrong
offset computation.
Also during the translation itself, the extra high part related to the
parent address is not present in the translated address.
Fix the "default-flags" map() and translate() in order to take into
account the child extra high address part in map() and the parent extra
high address part in translate() and so having a correct address
translation for ranges patterns such as the one given in the example
above.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Link: https://lore.kernel.org/r/20231017110221.189299-2-herve.codina@bootlin.com
Signed-off-by: Rob Herring <robh@kernel.org>
2023-10-17 13:02:16 +02:00
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2023-10-26 08:53:59 -05:00
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|
of: address: Fix address translation when address-size is greater than 2
With the recent addition of of_pci_prop_ranges() in commit 407d1a51921e
("PCI: Create device tree node for bridge"), the ranges property can
have a 3 cells child address, a 3 cells parent address and a 2 cells
child size.
A range item property for a PCI device is filled as follow:
<BAR_nbr> 0 0 <phys.hi> <phys.mid> <phys.low> <BAR_sizeh> <BAR_sizel>
<-- Child --> <-- Parent (PCI definition) --> <- BAR size (64bit) -->
This allow to translate BAR addresses from the DT. For instance:
pci@0,0 {
#address-cells = <0x03>;
#size-cells = <0x02>;
device_type = "pci";
compatible = "pci11ab,100", "pciclass,060400", "pciclass,0604";
ranges = <0x82000000 0x00 0xe8000000
0x82000000 0x00 0xe8000000
0x00 0x4400000>;
...
dev@0,0 {
#address-cells = <0x03>;
#size-cells = <0x02>;
compatible = "pci1055,9660", "pciclass,020000", "pciclass,0200";
/* Translations for BAR0 to BAR5 */
ranges = <0x00 0x00 0x00 0x82010000 0x00 0xe8000000 0x00 0x2000000
0x01 0x00 0x00 0x82010000 0x00 0xea000000 0x00 0x1000000
0x02 0x00 0x00 0x82010000 0x00 0xeb000000 0x00 0x800000
0x03 0x00 0x00 0x82010000 0x00 0xeb800000 0x00 0x800000
0x04 0x00 0x00 0x82010000 0x00 0xec000000 0x00 0x20000
0x05 0x00 0x00 0x82010000 0x00 0xec020000 0x00 0x2000>;
...
pci-ep-bus@0 {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "simple-bus";
/* Translate 0xe2000000 to BAR0 and 0xe0000000 to BAR1 */
ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
0xe0000000 0x01 0x00 0x00 0x1000000>;
...
};
};
};
During the translation process, the "default-flags" map() function is
used to select the matching item in the ranges table and determine the
address offset from this matching item.
This map() function simply calls of_read_number() and when address-size
is greater than 2, the map() function skips the extra high address part
(ie part over 64bit). This lead to a wrong matching item and a wrong
offset computation.
Also during the translation itself, the extra high part related to the
parent address is not present in the translated address.
Fix the "default-flags" map() and translate() in order to take into
account the child extra high address part in map() and the parent extra
high address part in translate() and so having a correct address
translation for ranges patterns such as the one given in the example
above.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Link: https://lore.kernel.org/r/20231017110221.189299-2-herve.codina@bootlin.com
Signed-off-by: Rob Herring <robh@kernel.org>
2023-10-17 13:02:16 +02:00
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2023-03-28 15:15:58 -05:00
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2020-07-30 08:56:14 +08:00
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2020-02-06 14:34:54 +00:00
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2021-04-15 15:00:51 -03:00
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2020-02-06 14:34:54 +00:00
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2010-06-08 07:48:10 -06:00
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2024-10-10 11:27:16 -05:00
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2020-08-19 10:42:55 +01:00
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2010-06-08 07:48:10 -06:00
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2013-07-03 16:01:10 +10:00
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2014-02-03 13:31:03 -02:00
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2013-07-03 16:01:10 +10:00
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2020-08-19 10:42:55 +01:00
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2013-07-03 16:01:10 +10:00
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2018-08-29 08:36:12 -05:00
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2020-08-19 10:42:55 +01:00
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2010-06-08 07:48:10 -06:00
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2012-10-08 19:41:58 -05:00
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2023-10-26 08:53:59 -05:00
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2010-06-08 07:48:10 -06:00
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2023-10-26 08:53:59 -05:00
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2010-06-08 07:48:10 -06:00
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2021-05-27 14:45:46 -05:00
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2010-06-08 07:48:10 -06:00
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2025-01-29 14:35:27 +01:00
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2024-09-06 14:25:19 +02:00
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2025-01-20 15:09:40 +01:00
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2024-09-06 14:25:19 +02:00
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2025-01-29 14:35:27 +01:00
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2024-09-06 14:25:19 +02:00
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2014-09-29 15:29:25 +01:00
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2023-03-31 09:52:29 +02:00
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2014-09-29 15:29:25 +01:00
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2024-10-10 11:27:16 -05:00
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2014-09-29 15:29:24 +01:00
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2024-09-06 14:25:19 +02:00
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2014-09-29 15:29:25 +01:00
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2014-09-29 15:29:24 +01:00
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2014-09-29 15:29:25 +01:00
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2018-03-15 02:15:52 +08:00
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2014-09-29 15:29:25 +01:00
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2024-09-06 14:25:19 +02:00
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2014-09-29 15:29:25 +01:00
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2024-09-06 14:25:19 +02:00
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2014-09-29 15:29:25 +01:00
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2024-09-06 14:25:19 +02:00
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2014-09-29 15:29:25 +01:00
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2014-09-29 15:29:24 +01:00
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2018-01-11 11:38:02 +05:30
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2010-06-08 07:48:10 -06:00
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2023-03-28 15:15:57 -05:00
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2024-09-06 14:25:19 +02:00
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2023-03-28 15:15:57 -05:00
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2010-06-08 07:48:10 -06:00
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2018-08-27 08:37:06 -05:00
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2010-06-08 07:48:10 -06:00
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2012-10-08 19:41:58 -05:00
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2023-10-26 08:53:59 -05:00
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2010-06-08 07:48:10 -06:00
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2010-12-01 10:54:46 +01:00
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2010-06-08 07:48:10 -06:00
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2023-10-26 08:53:59 -05:00
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2010-06-08 07:48:10 -06:00
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2010-12-01 10:54:46 +01:00
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2010-06-08 07:48:10 -06:00
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2010-12-01 10:54:46 +01:00
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2010-06-08 07:48:10 -06:00
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2023-03-28 15:15:58 -05:00
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2024-11-08 13:35:48 -06:00
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2023-03-28 15:15:58 -05:00
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2025-01-10 15:50:29 -06:00
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2010-06-08 07:48:10 -06:00
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2024-10-10 11:27:20 -05:00
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2018-01-17 17:36:39 -06:00
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2010-06-08 07:48:10 -06:00
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2023-10-17 13:02:17 +02:00
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2023-10-26 08:53:58 -05:00
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2010-06-08 07:48:10 -06:00
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2018-01-17 17:36:39 -06:00
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2010-06-08 07:48:10 -06:00
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2023-10-17 13:02:17 +02:00
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2023-10-26 08:53:58 -05:00
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2010-06-08 07:48:10 -06:00
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2023-03-28 15:15:58 -05:00
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of: address: Fix address translation when address-size is greater than 2
With the recent addition of of_pci_prop_ranges() in commit 407d1a51921e
("PCI: Create device tree node for bridge"), the ranges property can
have a 3 cells child address, a 3 cells parent address and a 2 cells
child size.
A range item property for a PCI device is filled as follow:
<BAR_nbr> 0 0 <phys.hi> <phys.mid> <phys.low> <BAR_sizeh> <BAR_sizel>
<-- Child --> <-- Parent (PCI definition) --> <- BAR size (64bit) -->
This allow to translate BAR addresses from the DT. For instance:
pci@0,0 {
#address-cells = <0x03>;
#size-cells = <0x02>;
device_type = "pci";
compatible = "pci11ab,100", "pciclass,060400", "pciclass,0604";
ranges = <0x82000000 0x00 0xe8000000
0x82000000 0x00 0xe8000000
0x00 0x4400000>;
...
dev@0,0 {
#address-cells = <0x03>;
#size-cells = <0x02>;
compatible = "pci1055,9660", "pciclass,020000", "pciclass,0200";
/* Translations for BAR0 to BAR5 */
ranges = <0x00 0x00 0x00 0x82010000 0x00 0xe8000000 0x00 0x2000000
0x01 0x00 0x00 0x82010000 0x00 0xea000000 0x00 0x1000000
0x02 0x00 0x00 0x82010000 0x00 0xeb000000 0x00 0x800000
0x03 0x00 0x00 0x82010000 0x00 0xeb800000 0x00 0x800000
0x04 0x00 0x00 0x82010000 0x00 0xec000000 0x00 0x20000
0x05 0x00 0x00 0x82010000 0x00 0xec020000 0x00 0x2000>;
...
pci-ep-bus@0 {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "simple-bus";
/* Translate 0xe2000000 to BAR0 and 0xe0000000 to BAR1 */
ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
0xe0000000 0x01 0x00 0x00 0x1000000>;
...
};
};
};
During the translation process, the "default-flags" map() function is
used to select the matching item in the ranges table and determine the
address offset from this matching item.
This map() function simply calls of_read_number() and when address-size
is greater than 2, the map() function skips the extra high address part
(ie part over 64bit). This lead to a wrong matching item and a wrong
offset computation.
Also during the translation itself, the extra high part related to the
parent address is not present in the translated address.
Fix the "default-flags" map() and translate() in order to take into
account the child extra high address part in map() and the parent extra
high address part in translate() and so having a correct address
translation for ranges patterns such as the one given in the example
above.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Link: https://lore.kernel.org/r/20231017110221.189299-2-herve.codina@bootlin.com
Signed-off-by: Rob Herring <robh@kernel.org>
2023-10-17 13:02:16 +02:00
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2010-06-08 07:48:10 -06:00
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2025-01-10 15:50:29 -06:00
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2010-06-08 07:48:10 -06:00
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2024-10-10 11:27:20 -05:00
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2010-06-08 07:48:10 -06:00
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2024-10-10 11:27:16 -05:00
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2014-11-14 17:55:03 +11:00
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2015-03-23 14:16:38 +11:00
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2014-11-14 17:55:03 +11:00
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2015-03-23 14:16:38 +11:00
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2014-11-14 17:55:03 +11:00
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2024-10-10 11:27:20 -05:00
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2010-06-08 07:48:10 -06:00
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2010-12-01 10:54:46 +01:00
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2010-06-08 07:48:10 -06:00
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2015-11-30 15:22:37 +09:00
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2010-06-08 07:48:10 -06:00
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2015-11-30 15:22:37 +09:00
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2010-06-08 07:48:10 -06:00
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2010-06-08 07:48:11 -06:00
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2019-09-04 11:43:30 +01:00
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2010-06-08 07:48:10 -06:00
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2019-09-04 11:43:30 +01:00
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2016-06-15 08:32:18 -05:00
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2010-06-08 07:48:11 -06:00
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2010-06-08 07:48:10 -06:00
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2024-11-24 11:05:37 +01:00
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2016-06-15 08:32:18 -05:00
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2010-06-08 07:48:10 -06:00
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2016-06-15 08:32:18 -05:00
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2010-06-08 07:48:10 -06:00
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2023-10-26 08:53:59 -05:00
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2010-06-08 07:48:10 -06:00
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2016-06-15 08:32:18 -05:00
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2010-06-08 07:48:10 -06:00
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2016-06-15 08:32:18 -05:00
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2021-06-16 11:27:45 +02:00
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2010-06-08 07:48:10 -06:00
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2018-03-15 02:15:54 +08:00
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2010-06-08 07:48:10 -06:00
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2024-04-09 13:59:41 -05:00
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2019-04-01 10:56:43 +02:00
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2018-03-15 02:15:54 +08:00
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2010-06-08 07:48:10 -06:00
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2024-04-09 13:59:41 -05:00
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2024-10-10 11:27:20 -05:00
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2012-10-08 19:41:58 -05:00
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2010-06-08 07:48:10 -06:00
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2017-06-01 15:50:55 -05:00
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2010-06-08 07:48:10 -06:00
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2018-03-15 02:15:54 +08:00
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2024-04-09 13:59:41 -05:00
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2010-06-08 07:48:10 -06:00
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2024-04-09 13:59:41 -05:00
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2010-06-08 07:48:10 -06:00
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2025-01-10 15:50:29 -06:00
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2010-06-08 07:48:10 -06:00
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2012-12-13 10:11:23 +00:00
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2010-06-08 07:48:10 -06:00
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2017-06-01 15:50:55 -05:00
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2024-04-09 13:59:41 -05:00
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2010-06-08 07:48:10 -06:00
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2010-06-08 07:48:10 -06:00
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2018-03-15 02:15:54 +08:00
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2010-06-08 07:48:10 -06:00
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2019-04-01 10:56:43 +02:00
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2010-06-08 07:48:10 -06:00
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2016-06-15 08:32:18 -05:00
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2010-06-08 07:48:10 -06:00
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2018-03-15 02:15:54 +08:00
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2018-03-15 02:15:54 +08:00
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2025-01-10 15:50:29 -06:00
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2010-06-08 07:48:10 -06:00
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2010-12-01 10:54:46 +01:00
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2018-03-15 02:15:54 +08:00
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2019-04-01 10:56:43 +02:00
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2018-03-15 02:15:54 +08:00
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2010-06-08 07:48:10 -06:00
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2022-09-29 13:48:38 +01:00
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2019-04-01 10:56:44 +02:00
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2024-12-06 08:52:30 +08:00
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2019-04-01 10:56:44 +02:00
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2022-09-29 13:48:38 +01:00
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2019-04-01 10:56:44 +02:00
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2019-07-03 18:23:01 +01:00
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2010-12-01 10:54:46 +01:00
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2010-06-08 07:48:10 -06:00
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2018-03-15 02:15:54 +08:00
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2019-04-01 10:56:44 +02:00
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2019-04-01 10:56:43 +02:00
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2018-03-15 02:15:54 +08:00
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2010-06-08 07:48:10 -06:00
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2023-01-20 18:42:48 +01:00
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2024-04-09 13:59:41 -05:00
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2023-01-20 18:42:48 +01:00
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2021-05-27 14:45:45 -05:00
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2010-06-08 07:48:10 -06:00
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2010-12-01 10:54:46 +01:00
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2010-06-08 07:48:10 -06:00
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2024-04-09 13:59:41 -05:00
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2024-10-10 11:27:20 -05:00
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2010-06-08 07:48:10 -06:00
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2024-04-09 13:59:41 -05:00
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2010-06-08 07:48:10 -06:00
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2025-01-10 15:50:29 -06:00
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2021-05-27 14:45:45 -05:00
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2024-04-09 13:59:41 -05:00
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2010-06-08 07:48:10 -06:00
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2024-11-08 13:35:48 -06:00
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2010-06-08 07:48:10 -06:00
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2021-05-27 14:45:45 -05:00
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2010-06-08 07:48:10 -06:00
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2021-05-27 14:45:45 -05:00
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2010-06-08 07:48:10 -06:00
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2021-05-27 14:45:45 -05:00
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2010-06-08 07:48:10 -06:00
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2023-03-28 15:16:00 -05:00
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2020-02-06 14:34:54 +00:00
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2026-07-27 10:36:59 +02:00
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2020-02-06 14:34:54 +00:00
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2020-02-06 14:01:05 +00:00
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2020-02-06 14:34:54 +00:00
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2020-07-28 23:36:55 +08:00
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2026-07-27 10:36:59 +02:00
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2020-02-06 14:34:54 +00:00
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2026-07-27 10:36:59 +02:00
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2020-02-06 14:34:54 +00:00
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2026-07-27 10:36:59 +02:00
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2020-02-06 14:34:54 +00:00
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2020-02-06 14:01:05 +00:00
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2020-02-06 14:34:54 +00:00
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2020-02-06 14:01:05 +00:00
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2026-07-27 10:36:59 +02:00
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2020-02-06 14:34:54 +00:00
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2020-02-06 14:01:05 +00:00
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2020-02-06 14:34:54 +00:00
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2026-07-27 10:36:59 +02:00
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2020-07-28 23:36:55 +08:00
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2020-02-06 14:01:05 +00:00
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2020-07-28 23:36:55 +08:00
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2020-02-06 14:01:05 +00:00
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2020-02-06 14:34:54 +00:00
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of: address: Add parent_bus_addr to struct of_pci_range
Add a new field called 'parent_bus_addr' to struct of_pci_range to use
when retrieving parent bus address information.
Refer to the diagram below to better understand that the bus fabric in
some systems (like i.MX8QXP) does not always use a 1:1 address map
between input and output.
Currently, many controller drivers use the cpu_addr_fixup() callback
that would often hardcode address translation directly in the code, e.g.,
"cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR" or "cpu_addr + BUS_IATU_OFFSET",
etc., even though those translations *should* be described via DT.
However, the cpu_addr_fixup() can be eliminated if DT correctly reflects
hardware behavior and drivers use 'parent_bus_addr' in struct of_pci_range.
┌─────────┐ ┌────────────┐
┌─────┐ │ │ IA: 0x8ff8_0000 │ │
│ CPU ├───►│ ┌────►├─────────────────┐ │ PCI │
└─────┘ │ │ │ IA: 0x8ff0_0000 │ │ │
CPU Addr │ │ ┌─►├─────────────┐ │ │ Controller │
0x7ff8_0000─┼───┘ │ │ │ │ │ │
│ │ │ │ │ │ │ PCI Addr
0x7ff0_0000─┼──────┘ │ │ └──► IOSpace ─┼────────────►
│ │ │ │ │ 0
0x7000_0000─┼────────►├─────────┐ │ │ │
└─────────┘ │ └──────► CfgSpace ─┼────────────►
BUS Fabric │ │ │ 0
│ │ │
└──────────► MemSpace ─┼────────────►
IA: 0x8000_0000 │ │ 0x8000_0000
└────────────┘
bus@5f000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x80000000 0x0 0x70000000 0x10000000>;
pcie@5f010000 {
compatible = "fsl,imx8q-pcie";
reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>,
<0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>;
...
};
};
In the diagram above, the 'parent_bus_addr' field in struct of_pci_range
can indicate internal address (IA) address information.
Link: https://lore.kernel.org/r/20241119-pci_fixup_addr-v8-1-c4bfa5193288@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-11-19 14:44:19 -05:00
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2020-02-06 14:34:54 +00:00
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2020-02-06 14:01:05 +00:00
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2020-02-06 14:34:54 +00:00
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2020-02-06 14:01:05 +00:00
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2020-07-28 23:36:55 +08:00
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2020-02-06 14:34:54 +00:00
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2020-07-28 23:36:55 +08:00
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2020-02-06 14:34:54 +00:00
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2020-07-28 23:36:55 +08:00
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2020-02-06 14:34:54 +00:00
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2020-02-06 14:01:05 +00:00
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2020-02-06 14:34:54 +00:00
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2018-03-15 02:15:54 +08:00
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2019-04-01 10:56:43 +02:00
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2018-03-15 02:15:54 +08:00
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2020-09-17 18:43:40 +02:00
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2014-04-24 11:30:02 -04:00
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2020-09-17 18:43:40 +02:00
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2014-04-24 11:30:02 -04:00
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2020-09-17 18:43:40 +02:00
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2014-04-24 11:30:02 -04:00
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2020-09-17 18:43:40 +02:00
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2014-04-24 11:30:02 -04:00
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2020-09-17 18:43:40 +02:00
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2014-04-24 11:30:02 -04:00
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2020-09-17 18:43:40 +02:00
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2014-04-24 11:30:02 -04:00
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2024-04-09 13:59:41 -05:00
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2014-04-24 11:30:02 -04:00
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2019-07-03 18:42:20 +01:00
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2020-02-06 14:02:30 +00:00
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2020-09-17 18:43:40 +02:00
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2014-04-24 11:30:02 -04:00
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2019-07-03 18:42:20 +01:00
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2014-04-24 11:30:02 -04:00
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2019-07-03 18:42:20 +01:00
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2024-04-09 13:59:41 -05:00
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2019-07-03 18:42:20 +01:00
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2014-04-24 11:30:02 -04:00
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2019-07-03 18:42:20 +01:00
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2017-06-01 15:50:55 -05:00
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2024-04-09 13:59:41 -05:00
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2014-04-24 11:30:02 -04:00
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2020-02-06 14:02:30 +00:00
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2023-01-28 17:47:50 +00:00
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2020-09-17 18:43:40 +02:00
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2023-01-28 17:47:50 +00:00
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2024-04-09 13:59:41 -05:00
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2020-02-06 14:02:30 +00:00
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2026-02-21 16:37:42 -08:00
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2024-04-09 13:59:41 -05:00
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2020-09-17 18:43:40 +02:00
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2023-01-28 17:47:50 +00:00
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2020-09-17 18:43:40 +02:00
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2020-02-06 14:02:30 +00:00
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2023-01-28 17:47:50 +00:00
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2020-08-17 12:32:08 +01:00
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2020-09-17 18:43:40 +02:00
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2020-02-06 14:26:40 +00:00
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2024-04-09 13:59:41 -05:00
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2014-04-24 11:30:02 -04:00
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2020-09-17 18:43:40 +02:00
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2014-04-24 11:30:03 -04:00
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2020-11-19 18:53:55 +01:00
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2026-07-27 10:36:59 +02:00
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2020-11-19 18:53:55 +01:00
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2014-04-24 11:30:03 -04:00
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2020-01-26 22:52:47 +11:00
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2022-07-07 01:15:33 +02:00
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2014-04-24 11:30:03 -04:00
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2024-04-09 13:59:41 -05:00
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2020-11-10 15:28:25 +13:00
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2014-04-24 11:30:03 -04:00
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2024-04-09 13:59:41 -05:00
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2019-07-03 14:47:31 +01:00
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2014-04-24 11:30:03 -04:00
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2024-04-09 13:59:41 -05:00
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2014-04-24 11:30:03 -04:00
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2014-06-05 15:57:04 -07:00
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2021-02-11 21:41:56 +09:00
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2024-10-10 11:27:16 -05:00
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2021-02-11 21:41:56 +09:00
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2024-04-09 13:59:41 -05:00
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2021-02-11 21:41:56 +09:00
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2025-03-19 15:25:58 +01:00
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2021-02-11 21:41:56 +09:00
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2023-03-31 09:52:30 +02:00
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2024-09-06 14:25:19 +02:00
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2023-03-31 09:52:30 +02:00
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