drm/i915: Force common lane on for the PPS kick on CHV

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With DPIO powergating active the DPLL can't be accessed unless
something else is keeping the common lane in the channel on.
That means the PPS kick procedure could fail to enable the PLL.

Power up some data lanes to force the common lane to power up
so that the PLL can be enabled temporarily.

v2: Avoid gcc uninitilized variable warning

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Ville Syrjälä 2015-07-10 10:56:24 +03:00 • committed by Daniel Vetter

parent b0b3384612

commit 0047eedc48

1 changed files with 13 additions and 3 deletions

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drivers/gpu/drm/i915/intel_dp.c

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