From 011242de59d0eb69e7b8a4f42dc32cf1f5d53592 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Jul 2026 22:12:13 +0800 Subject: [PATCH] arm64: dts: imx8ulp-evk: Add gpio-keys node for power button Add a gpio-keys node for the power-on button, report it as KEY_POWER to user space. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8ulp-9x9-evk.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 19 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts index 5497e3d78136..af8f0d6087f7 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts @@ -10,6 +10,18 @@ / { model = "NXP i.MX8ULP EVK9"; compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + button-power-on { + label = "PowerOn"; + gpios = <&gpiof 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; }; &btcpu { @@ -43,6 +55,12 @@ >; }; +&pinctrl_gpio_keys { + fsl,pins = < + MX8ULP_PAD_PTF11__PTF11 0x3 + >; +}; + &pinctrl_usb1 { fsl,pins = < MX8ULP_PAD_PTE16__USB0_ID 0x10003 diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 5dea66c1e7aa..6a92c5ca9a41 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "imx8ulp.dtsi" / { @@ -20,6 +21,18 @@ stdout-path = &lpuart5; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + button-power-on { + label = "PowerOn"; + gpios = <&gpiof 31 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0 0x80000000>; @@ -323,6 +336,12 @@ >; }; + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX8ULP_PAD_PTF31__PTF31 0x3 + >; + }; + pinctrl_lpuart5: lpuart5grp { fsl,pins = < MX8ULP_PAD_PTF14__LPUART5_TX 0x3