ASoC: Fix WM8993 MCLK configuration for high frequency MCLKs

When used without the PLL we were accidentally clearing the MCLK/2
divider, resulting in a double rate SYSCLK when the divider should
have been used.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Mark Brown 2009-08-17 18:51:44 +01:00
commit 0182dcc52c