phy: fsl-imx8mq-usb: add control register regmap

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The CR port is a simple 16-bit data/address parallel port that is
accessed through 32-bit MMIO registers for on-chip access to the
control registers inside the USB 3.0 femtoPHY. Add control register
regmap and export these registers by debugfs to help PHY's diagnostic.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Link: https://patch.msgid.link/20260731-imx8mp-usb-phy-improvement-v8-4-2ec8d6b3854d@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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Xu Yang 2026-07-31 16:11:22 +08:00 • committed by Vinod Koul

parent 56eec5d966

commit 01e9e84a43

2 changed files with 27 additions and 1 deletions

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drivers/phy/freescale/Kconfig

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27

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

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