drm/i915/guc/slpc: Cache platform frequency limits

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Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.

Also add "soft" limits which keep track of frequency changes
made from userland. These are initially set to platform min
and max.

v2: Address review comments (Michal W)
v3: Formatting (Michal W)
v4: Add separate function to parse rp values (Michal W)
v5: Perform range checking for set min/max (Michal W)
v6: checkpatch() and rename static functions (Michal W)
v7: check ret code while setting SLPC limits (Michal W)

Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210730202119.23810-12-vinay.belgaumkar@intel.com

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This commit is contained in:

Vinay Belgaumkar 2021-07-30 13:21:16 -07:00 • committed by John Harrison

parent 899a0fd73a

commit 025cb07beb

3 changed files with 151 additions and 0 deletions

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139

drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c

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9

drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h

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3

drivers/gpu/drm/i915/i915_reg.h

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