ARM: dts: qcom: sdx65: Add support for A7 PLL clock

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On SDX65 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-4-git-send-email-quic_rohiagar@quicinc.com

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Rohit Agarwal 2022-02-22 10:26:23 +05:30 • committed by Bjorn Andersson

parent c20aa951ee

commit 02c5553523

1 changed files with 8 additions and 0 deletions

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arch/arm/boot/dts/qcom-sdx65.dtsi

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