drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.

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On Broadwell, any PIPE_CONTROL with the "State Cache Invalidate" bit set
must be preceded by a PIPE_CONTROL with the "CS Stall" bit set.

Documented on the BSpec 3D workarounds page.

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
[vsyrjala: add chv w/a note too]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

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Kenneth Graunke 2014-01-27 14:20:16 -08:00 • committed by Daniel Vetter

parent 884ceacee3

commit 02c9f7e3cf

1 changed files with 9 additions and 0 deletions

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drivers/gpu/drm/i915/intel_ringbuffer.c

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