drm/msm/a6xx: update pdc/rscc GMU registers for A640/A650

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Update the gmu_pdc registers for A640 and A650.

Some of the RSCC registers on A650 are in a separate region.

Note this also changes the address of these registers:

RSCC_TCS1_DRV0_STATUS
RSCC_TCS2_DRV0_STATUS
RSCC_TCS3_DRV0_STATUS

Based on the values in msm-4.14 and msm-4.19 kernels.

v3: replaced adreno_is_a650 around ->rscc with checks for "rscc" resource

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

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Jonathan Marek 2020-04-23 17:09:19 -04:00 • committed by Rob Clark

parent c6ed04f856

commit 02ef80c54e

3 changed files with 85 additions and 53 deletions

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90

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

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10

drivers/gpu/drm/msm/adreno/a6xx_gmu.h

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38

drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h

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