soc: imx: imx8mp-blk-ctrl: enable global pixclk with HDMI_TX_PHY PD

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[ Upstream commit b814eda949 ]

NXP internal information shows that the PHY refclk is gated by the
GLOBAL_TX_PIX_CLK_EN bit, so to allow the PHY PLL to lock without the
LCDIF being already active, tie this bit to the HDMI_TX_PHY power
domain.

Fixes: e3442022f5 ("soc: imx: add i.MX8MP HDMI blk-ctrl")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

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Lucas Stach 2022-12-31 13:40:25 +08:00 • committed by Greg Kroah-Hartman

parent 8aa234b1a4

commit 02ef93c4df

1 changed files with 4 additions and 2 deletions

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drivers/soc/imx/imx8mp-blk-ctrl.c

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