x86, mce, cmci: define MSR names and fields for new CMCI registers

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Impact: New register definitions only

CMCI means support for raising an interrupt on a corrected machine
check event instead of having to poll for it. It's a new feature in
Intel Nehalem CPUs available on some machine check banks.

For details see the IA32 SDM Vol3a 14.5

Define the registers for it as a preparation for further patches.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>

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Andi Kleen 2009-02-12 13:49:35 +01:00 • committed by H. Peter Anvin

parent ee031c31d6

commit 03195c6b40

3 changed files with 8 additions and 0 deletions

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1

arch/x86/include/asm/apicdef.h

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2

arch/x86/include/asm/mce.h

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5

arch/x86/include/asm/msr-index.h

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