clk: mxs: Fix invalid 32-bit access to frac registers

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According to i.MX23 and i.MX28 reference manual [1],[2] the fractional
clock control register is 32-bit wide, but is separated in 4 parts.
So write instructions must not apply to more than 1 part at once.

The clk init for the i.MX28 violates this restriction and all the other
accesses on that register suggest that there isn't such a restriction.

This patch restricts the access to this register to byte instructions and
extends the comment in the init functions.

Btw the imx23 init now uses a R-M-W sequence just like imx28 init
to avoid any clock glitches.

The changes has been tested with a i.MX23 and a i.MX28 board.

[1] - http://cache.freescale.com/files/dsp/doc/ref_manual/IMX23RM.pdf
[2] - http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdf

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

...

This commit is contained in:

Stefan Wahren 2015-01-30 19:20:10 +00:00 • committed by Michael Turquette

parent 6793a30a06

commit 039e597075

3 changed files with 31 additions and 18 deletions

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11

drivers/clk/mxs/clk-imx23.c

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19

drivers/clk/mxs/clk-imx28.c

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19

drivers/clk/mxs/clk-ref.c

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