drm/i915: Use documented PLL timing limits for G4X platform

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The values come from the internal reference spreadsheet on PLL
timing limits for the G4X chipsets.

Part of fixing fd.o bug #17508

Signed-off-by: Ma Ling <ling.ma@intel.com>
[anholt: Cleaned up some whitespace]
Signed-off-by: Eric Anholt <eric@anholt.net>

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Ma Ling 2009-03-18 20:13:23 +08:00 • committed by Eric Anholt

parent 568d9a8f6d

commit 044c7c415a

1 changed files with 186 additions and 1 deletions

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187

drivers/gpu/drm/i915/intel_display.c

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