drm/xe/sysctrl: Read mailbox phase bit from hardware

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The mailbox PHASE bit in SYSCTRL_MB_CTRL is toggled per-message and
was tracked in software as sc->phase_bit, reset to 0 on error paths.
If the cached value ever drifts from what the hardware last saw, all
following messages carry the wrong phase and get silently misread by
firmware.

Drop the cache and read PHASE directly from SYSCTRL_MB_CTRL before
each frame instead, removing xe_sysctrl_mailbox_init() and its call
sites along with it.

Fixes: 1f95f61818 ("drm/xe/xe_sysctrl: Add System Controller mailbox communication support")
Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/20260825172827.3801591-2-anoop.c.vijay@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

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Anoop Vijay 2026-08-25 10:28:28 -07:00 • committed by Rodrigo Vivi

parent 76cc14e2fa

commit 04984fcdbf

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GPG key ID: FA625F640EEB13CA

4 changed files with 5 additions and 28 deletions

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7

drivers/gpu/drm/xe/xe_sysctrl.c

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22

drivers/gpu/drm/xe/xe_sysctrl_mailbox.c

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1

drivers/gpu/drm/xe/xe_sysctrl_mailbox.h

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3

drivers/gpu/drm/xe/xe_sysctrl_types.h

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