drm/i915/dg1: Add DPLL macros for DG1

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DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
DPLL2 and DPLL3 drive DDI-TC1/DDI-TC2.

Introduce DG1_DPLL_CFCRx() helper macros to configure
DPLL registers.

Bspec: 50288, 50299

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-4-lucas.demarchi@intel.com

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Aditya Swarup 2020-10-14 12:19:30 -07:00 • committed by Lucas De Marchi

parent 240abb3c76

commit 049c651b6d

2 changed files with 33 additions and 1 deletions

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17

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

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17

drivers/gpu/drm/i915/i915_reg.h

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