drm/msm/a6xx: Poll AHB fence status in GPU IRQ handler

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Even though the GX power domain is kept ON when there is a pending GPU
interrupt, there is a small window of potential race with GMU where it
may move the AHB fence to 'Drop' mode. Once the GMU sees the pending IRQ,
it will move back the fence state to ALLOW mode. Close this race window
by polling for AHB fence to ensure that it is in 'Allow' mode.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673377/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

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Akhil P Oommen 2025-09-08 13:57:03 +05:30 • committed by Rob Clark

parent f195421318

commit 04ca842ef2

2 changed files with 29 additions and 0 deletions

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3

drivers/gpu/drm/msm/adreno/a6xx_gmu.h

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26

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

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