arm64: dts: k3-j721e-proc-board: Add wait time for sampling Type-C DIR line

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The Type-C compainon chip on the board needs ~133ms (tCCB_DEFAULT)
to debounce the CC lines in order to detect attach and plug orientation
and reflect the correct DIR status. [1]

On the EVM however we need to wait upto 700ms before sampling the
Type-C DIR line else we can get incorrect direction state.

[1] http://www.ti.com/lit/ds/symlink/tusb321.pdf

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

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Roger Quadros 2020-06-29 15:52:54 +03:00 • committed by Tero Kristo

parent 02c35dca2b

commit 04fe6477ef

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arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts

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