clk: meson: add fdiv clock gates

Fdiv fixed dividers clocks of the fixed_pll can actually gate independently. We never had an issue so far because these clocks were provided 'enabled' by the bootloader. Add these gates to enable/disable the clocks when required. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2026-10-12 06:01:58 +00:00 · 2018-02-19 12:21:45 +01:00 · 2018-02-19 12:21:45 +01:00 · 05f814402d
commit 05f814402d
parent 513b67ac39
6 changed files with 278 additions and 33 deletions
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h