clk: mmp: frac: Do not lose last 4 digits of precision

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While calculating the output rate of a fractional divider clock, the
value is divided and multipled by 10000, discarding the least
significant digits -- presumably to fit the intermediate value within 32
bits.

The precision we're losing is, however, not insignificant for things like
I2S clock. Maybe also elsewhere, now that since commit ea56ad6026 ("clk:
mmp2: Stop pretending PLL outputs are constant") the parent rates are more
precise and no longer rounded to 10000s.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200519224151.2074597-2-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

...

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Lubomir Rintel 2020-05-20 00:41:39 +02:00 • committed by Stephen Boyd

parent 8f3d9f3542

commit 06030c4e33

1 changed files with 16 additions and 8 deletions

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drivers/clk/mmp/clk-frac.c

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