drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1

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[WHY]
In certain conditions with low pixel clock, some values in DML may go
past the max due to margining for latency hiding. This causes assertions
to get hit.

[HOW]
If the pixel clock is low and some values are high, cap it to the max.

Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Sung Lee 2020-03-25 14:44:25 -04:00 • committed by Alex Deucher

parent bccbf13dad

commit 06535a48e2

1 changed files with 10 additions and 2 deletions

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drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

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