clk: renesas: Add support for R9A09G077 SoC

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RZ/T2H has 2 register blocks at different addresses.

The clock tree has configurable dividers and mux selectors.
Add these new clock types, new register layout type, and
registration code for mux and div in registration callback.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250515141828.43444-6-thierry.bultel.yh@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Thierry Bultel 2025-05-15 16:18:20 +02:00 • committed by Geert Uytterhoeven

parent e5e8a9cce5

commit 065fe720ee

5 changed files with 346 additions and 2 deletions

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5

drivers/clk/renesas/Kconfig

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1

drivers/clk/renesas/Makefile

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241

drivers/clk/renesas/r9a09g077-cpg.c

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89

drivers/clk/renesas/renesas-cpg-mssr.c

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12

drivers/clk/renesas/renesas-cpg-mssr.h

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