drm/i915/display: Add 480 MHz CDCLK steps for RPL-U

Browse source

A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.

v2: (Matt)
    - Add missing clock steps
    - Correct reference clock typo

v3: - Revert to RPL-U subplatform (Jani)

v4: - Remove Bspec reference from code (Jani)

Bspec: 55409
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230130100806.1373883-3-chaitanya.kumar.borah@intel.com

...

This commit is contained in:

Chaitanya Kumar Borah 2023-01-30 15:38:06 +05:30 • committed by Jani Nikula

parent 61b795a9c3

commit 06f1b06dc5

1 changed files with 26 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

26

drivers/gpu/drm/i915/display/intel_cdclk.c

View file