drm/i915/chv: Trigger phy common lane reset

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During cold boot, the display controller needs to deassert the common
lane reset.  Only do it once during intel_init_dpio for both PHYx2 and
PHYx1.

Besides, assert the common lane reset when disable pll.  This still
to be determined whether need to do it by driver.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
[vsyrjala: Don't disable DPIO PLL when using DSI]
[vsyrjala: Don't call vlv_disable_pll() by accident on CHV]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
[danvet: Move part of a moved comment back as suggested by Imre since
it's valid for both byt and chv.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

This commit is contained in:

Chon Ming Lee 2014-04-09 13:28:17 +03:00 • committed by Daniel Vetter

parent eb69b0e59a

commit 076ed3b295

2 changed files with 65 additions and 15 deletions

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8

drivers/gpu/drm/i915/i915_reg.h

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72

drivers/gpu/drm/i915/intel_display.c

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