drm/i915: Split GAM and MSLICE steering

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Although the bspec lists several MMIO ranges as "MSLICE," it turns out
that a subset of these are of a "GAM" subclass that has unique rules and
doesn't followed regular mslice steering behavior.

 * Xe_HP SDV:  GAM ranges must always be steered to 0,0.  These
   registers share the regular steering control register (0xFDC) with
   other steering types

 * DG2:  GAM ranges must always be steered to 1,0.  GAM registers have a
   dedicated steering control register (0xFE0) so we can set the value
   once at startup and rely on implicit steering.  Technically the
   hardware default should already be set to 1,0 properly, but it never
   hurts to ensure that in the driver.

Bspec: 66534
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220916014345.3317739-1-matthew.d.roper@intel.com

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This commit is contained in:

Matt Roper 2022-09-15 18:43:45 -07:00

parent fb78189899

commit 07a70f38e9

4 changed files with 34 additions and 2 deletions

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24

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

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1

drivers/gpu/drm/i915/gt/intel_gt_regs.h

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1

drivers/gpu/drm/i915/gt/intel_gt_types.h

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10

drivers/gpu/drm/i915/gt/intel_workarounds.c

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