coresight-tpdm: Add support to select lane

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TPDM MCMB subunits supports up to 8 lanes CMB. For MCMB
configurations, the field "XTRIG_LNSEL" in CMB_CR register selects
which lane participates in the output pattern mach cross trigger
mechanism governed by the M_CMB_DXPR and M_CMB_XPMR regisers.

Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250226064008.2531037-3-quic_jinlmao@quicinc.com

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Tao Zhang 2025-02-25 22:40:07 -08:00 • committed by Suzuki K Poulose

parent ee39dbe939

commit 07f7c21745

3 changed files with 62 additions and 0 deletions

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8

Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm

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51

drivers/hwtracing/coresight/coresight-tpdm.c

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3

drivers/hwtracing/coresight/coresight-tpdm.h

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