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Amlogic clock updates for v5.8:
* Meson8b: Updates and fixup HDMI and video clocks * Meson8b: Fixup reset polarity * Meson gx and g12: fix GPU glitch free mux switch -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAl65FtsACgkQ5vwPHDfy 2oVVJg//Y9BujygiryGeaSbFt0c4LzVVBq3phce8SQ5Y2NBmlUGJ7KmZiywwI4MU T8lDBMY5cpBOCvulrWCYX/hggU0P6Ejz8h8hbHFwOPJH2YoC9EyID/dZJlKaWnCl aMohhUYQ5GxRve4Iddwu8u6Xb+p+fEmcHbVB4EAoP9UlBdxgpbEHuLtFmQjFZqjb GfFxy/pa4+LKDGjPCp6k6kbjsanWWB7B8S7V7MNQcy058rMKqsnep4boBrR5suoh U6ZS5mPoj4ZDx0rRaCCjZdhaUvVf8YPog9klg3hGGXmqAVtLuhf8ZaJiwYLrlIew qnxslb88kQtcnAlr5S0bM2JTTtlR9wBJqhhe53U19y2F82H5C1vbO+5hlehzj5/9 LFW09rlLtns71G9hX5ma9UHy0gDw4qnMWmg7r61jmpk5wJ9sdKoHB42qHPmQKUCv RwlWVUy2Lac7jgrVhVR7wS2NE+16dYEjK66nhbFvXS+j+WMBjLOOrJooCxUSb5R9 xPHtjB99dFwFH9COWxSFmMQAv8HEvEOnOf4tgrMOk6TQqfFoOeueaRO6WsFMj9kj 3hIO3ys8WaFG3pUfTviql+/d1AThDoRKv8N+a3257roa2Ljx4MohieBHQjO8CWVR K7zDMMBxilsT8ysgth7owrhKSPhE/ZLh/7T6gXGlmcKb4PRH2pA= =9+gg -----END PGP SIGNATURE----- Merge tag 'clk-meson-v5.8-1' of https://github.com/BayLibre/clk-meson into clk-amlogic Pull Amlogic clk driver updates from Jerome Brunet: - Meson8b: Updates and fixup HDMI and video clocks - Meson8b: Fixup reset polarity - Meson gx and g12: fix GPU glitch free mux switch * tag 'clk-meson-v5.8-1' of https://github.com/BayLibre/clk-meson: clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers clk: meson: meson8b: Make the CCF use the glitch-free VPU mux clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits clk: meson: meson8b: Fix the polarity of the RESET_N lines clk: meson: meson8b: Fix the first parent of vid_pll_in_sel clk: meson: g12a: Prepare the GPU clock tree to change at runtime clk: meson: gxbb: Prepare the GPU clock tree to change at runtime clk: meson: meson8b: make the hdmi_sys clock tree mutable clk: meson8b: export the HDMI system clock
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