drm/amd/display: Fix detection of 4 lane for DPALT

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[Why]
DPALT detection for B0 PHY has its own set of RDPCSPIPE registers

[How]
Use RDPCSPIPE registers to detect if DPALT lane is 4 lane

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Hansen <Hansen.Dsouza@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Hansen 2021-10-01 22:36:15 +08:00 • committed by Alex Deucher

parent aa635f6509

commit 07fe77c3ad

2 changed files with 35 additions and 1 deletions

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33

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c

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3

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h

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