KVM: PPC: E500: Ignore L1CSR1_ICFI,ICLFR

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The L1 instruction cache control register contains bits that indicate
that we're still handling a request. Mask those out when we set the SPR
so that a read doesn't assume we're still doing something.

Signed-off-by: Alexander Graf <agraf@suse.de>

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Alexander Graf 2014-04-17 12:53:13 +02:00

parent 1f85411255

commit 07fec1c2e7

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arch/powerpc/kvm/e500_emulate.c

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