clk: ti: omap5+: dpll: implement errata i810

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Errata i810 states that DPLL controller can get stuck while transitioning
to a power saving state, while its M/N ratio is being re-programmed.

As a workaround, before re-programming the M/N ratio, SW has to ensure
the DPLL cannot start an idle state transition. SW can disable DPLL
idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request
active by setting a dependent clock domain in SW_WKUP.

This errata impacts OMAP5 and DRA7 chips, so enable the errata for these.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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Tero Kristo 2015-11-30 16:43:25 +02:00 • committed by Stephen Boyd

parent cf81a1cf71

commit 07ff73a932

3 changed files with 29 additions and 1 deletions

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include/linux/clk/ti.h

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