From 080b14b09ee5bfafe91963adb79b4816dc21c9a2 Mon Sep 17 00:00:00 2001 From: Meera Patel Date: Tue, 28 Apr 2026 12:49:41 -0400 Subject: [PATCH] drm/amd/display: Fix DPREFCLK override when SMU isn't present or ready for DCN315 [Why] If SMU has not loaded properly or is not present in a test environment, then the DPREFCLK is overridden with an invalid value. [How] Add an SMU present check and shift the override below the check. Reviewed-by: Dmytro Laktyushkin Signed-off-by: Meera Patel Signed-off-by: Dmytro Laktyushkin Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c index 6ba7cff2ce05..8ca367b72325 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c @@ -673,16 +673,16 @@ void dcn315_clk_mgr_construct( &clk_mgr->base.base, &log_info); clk_mgr->base.base.dprefclk_khz = 600000; - clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base); clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; dcn10_clock_read_ss_info(&clk_mgr->base); clk_mgr->base.base.clks.ref_dtbclk_khz = dcn10_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz); clk_mgr->base.base.bw_params = &dcn315_bw_params; - if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) { + if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled && clk_mgr->base.smu_present) { int i; + clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base); dcn315_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks); DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n" "NumDispClkLevelsEnabled: %d\n"